參數(shù)資料
型號: T89C51CC02CA-TISIM
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Enhanced 8-bit Microcontroller with CAN Controller and Flash
中文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PDSO28
封裝: 0.300 INCH, PLASTIC, SOIC-28
文件頁數(shù): 135/170頁
文件大?。?/td> 1927K
代理商: T89C51CC02CA-TISIM
135
A/T89C51CC01
4129L–CAN–08/05
ADC Converter
Operation
A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).
After completion of the A/D conversion, the ADSST bit is cleared by hardware.
The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is
available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is
set, an interrupt occur when flag ADEOC is set (see Figure 62). Clear this flag for re-
arming the interrupt.
The bits SCH0 to SCH2 in ADCON register are used for the analog input channel
selection.
(1)
Note:
1. Always leave Tsetup time before starting a conversion unless ADEN is permanently
high. In this case one should wait Tsetup only before the first conversion.
Table 107.
Selected Analog input
Voltage Conversion
When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If
the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between
VAREF and VAGND are a straight-line linear conversion. All other voltages will result in
3FFh if greater than VAREF and 000h if less than VAGND.
Note:
ADCIN should not exceed VAREF absolute maximum range (see “Absolute Maximum
Ratings” on page 148)
Clock Selection
The ADC clock is the same as CPU.
The maximum clock frequency is defined in the DC parmeters for A/D converter. A pres-
caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency.
f
ADC
=
fcpu clock/ (4 (or 2 in X2 mode)* PRS )
with
if PRS > 0 then f
ADC
=
F
periph
/ 2 x PRS
if PRS = 0 then f
ADC
=
F
periph
/ 64
SCH2
SCH1
SCH0
Selected Analog input
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
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