參數(shù)資料
型號: T89C51CC01
廠商: Atmel Corp.
英文描述: Enhanced 8-bit MCU with CAN controller and Flash
中文描述: 增強型8位微控制器的CAN控制器和Flash
文件頁數(shù): 102/170頁
文件大小: 1927K
代理商: T89C51CC01
102
A/T89C51CC01
4129L–CAN–08/05
Table 60.
CANGIT Register
CANGIT (S:9Bh)
CAN General Interrupt
Note:
1. These fields are Read Only.
Reset Value = 0x00 0000b
7
6
5
4
3
2
1
0
CANIT
-
OVRTIM
OVRBUF
SERG
CERG
FERG
AERG
Bit
Number
Bit Mnemonic Description
7
CANIT
General Interrupt Flag
(1)
This status bit is the image of all the CAN controller interrupts sent to the
interrupt controller.
It can be used in the case of the polling method.
6
-
Reserved
The values read from this bit is indeterminate. Do not set this bit.
5
OVRTIM
Overrun CAN Timer
This status bit is set when the CAN timer switches 0xFFFF to 0x0000.
If the bit ETIM in the IE1 register is set, an interrupt is generated.
Clear this bit in order to reset the interrupt.
4
OVRBUF
Overrun BUFFER
0 - no interrupt.
1 - IT turned on
This bit is set when the buffer is full.
Bit resetable by user.
see Figure 46.
3
SERG
Stuff Error General
Detection of more than five consecutive bits with the same polarity.
This flag can generate an interrupt. resetable by user.
2
CERG
CRC Error General
The receiver performs a CRC check on each destuffed received message
from the start of frame up to the data field.
If this checking does not match with the destuffed CRC field, a CRC error is
set.
This flag can generate an interrupt. resetable by user.
1
FERG
Form Error General
The form error results from one or more violations of the fixed form in the
following bit fields:
CRC delimiter
acknowledgment delimiter
end_of_frame
This flag can generate an interrupt. resetable by user.
0
AERG
Acknowledgment Error General
No detection of the dominant bit in the acknowledge slot.
This flag can generate an interrupt. resetable by user.
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