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參數(shù)資料
| 型號(hào)： | T8532 |
| 廠商： | Lineage Power |
| 元件分類： | Codec |
| 英文描述： | Multichannel Programmable Codec Chip Set(多通道可編程編解碼器芯片組) |
| 中文描述： | 多通道可編程解碼器芯片組（多通道可編程編解碼器芯片組） |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大小： | 203K |
| 代理商： | T8532 |
Product Brief
June 2000
T8531/T8532 Multichannel Programmable Codec Chip Set
Features
I
Single 5 V power supply operation
I
Per-channel programmable transmit gain
— 25.6 dB range, better than 0.01 dB steps
I
Per-channel programmable receive gain
— 17.8 dB range, better than 0.01 dB steps
I
Per-channel programmable hybrid balance
I
Programmable termination impedances
I
Programmable
μ
-law, A-law, or linear PCM output
I
DTMF generator
I
DTMF receiver
I
Caller ID generator
I
Call progress tones generator
I
Automatic gain calibration
I
Programmable time-slot assignment with bit offset
I
Low-noise, balanced, receive SLIC interface
I
Few or no SLIC/codec interface components
required
I
Analog and digital loopbacks
I
Sigma-delta converters with dither noise reduction
I
Serial microcontroller control interface
I
Available in 64-pin MQFP and TQFP packages
Description
The Multichannel Programmable Codec Chip Set is
comprised of the T8531 16-channel line card signal
processor and one or two custom T8532 octal A/D
and D/A converters. A ROM-coded tone plant is
included on the signal processor. Together these
devices achieve a highly integrated and highly pro-
grammable multichannel voice codec solution.
The
T8531 contains a digital signal processor (DSP)
engine surrounded by a customized input/output
frame. DSP ROM memory holds DTMF transceiver,
caller line identification, and call progress tone algo-
rithms for use on a per-channel basis. The I/O frame
performs the
μ
-law or A-law conversion as well as
the decimation and interpolation functions needed to
interface the sigma-delta bit streams to the digital
signal processor engine. The sigma-delta converters
operate at a 1.024 MHz sample rate, while the signal
processor operates at 16 ksamples/s. A key function
of the I/O frame is to control the timing of the digital
data going to the signal processor so that group
delay is minimized.
The I/O frame also contains an integrated phase-
locked loop which synthesizes all the required inter-
nal clocks for the chip set.
The microcontroller interface is used to run the ROM
routines and to download the gain, filter, and balance
network settings, powerup/powerdown commands,
time-slot assignments, digital loopback settings, and
commands for the T8532 octal chips.
Each of the T8532’s channels consists of an antialias
filter, sigma-delta A/D and D/A converters, recon-
struction and smoothing filters, termination imped-
ance synthesis, and selectable gain. The digital
oversampled data is multiplexed onto a serial data
port designed to interface with the T8531. Another
serial interface accepts control data from the T8531
for activating the various gain settings, self-test, and
powerdown modes. This chip also contains a preci-
sion voltage reference.
Software is provided to compute the gain and filter
coefficients required to program the codec.
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