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參數(shù)資料
| 型號： | T7906EKTSV |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single Point to Point IEEE 1355 High Speed Controller |
| 中文描述： | 3 CHANNEL(S), 200M bps, SERIAL COMM CONTROLLER, CQFP100 |
| 封裝： | CERAMIC, MQFP-100 |
| 文件頁數(shù)： | 9/42頁 |
| 文件大?。?/td> | 339K |
| 代理商： | T7906EKTSV |
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9
T7906E
Rev. A
–
27-Aug.-01
IOB Control Bus
The allocation of the I/O busses is shown in the table below:
GPIO Signals
The pins GPIO0 to GPIO7 are either mapped on register GPIO0 (0x63 / 0x64) or miscel-
laneous I/O signals, depending on the register settings as shown in the table below:
Signal
Function
Signal
Function
Signal
Function
RAM Interface
I/O
ADC/DAC/FIFO Interface
I/O
GPIO
IOB[7:0]
RAM_ADDR[7:0]
O
ADC_ADDR[7:0]
O
GPIO1[7:0]
IOB8
RAM_ADDR8
O
ADC_CS*
O
IOB9
RAM_ADDR9
O
ADC_R/C*
O
IOB10
RAM_ADDR10
O
DAC_WR*
O
IOB11
RAM_ADDR11
O
DAC_ADDR0
O
IOB12
RAM_ADDR12
O
DAC_ADDR1
O
IOB13
RAM_ADDR13
O
DAC_ADDR2
O
IOB14
RAM_ADDR14
O
FIFO_TRM_EOP_ACK
O
IOB15
RAM_ADDR15
O
FIFO_RCV_PAR
O
IOB16
RAM_WR*
O
FIFO_RCV_EOP1
O
IOB17
RAM_RD*
O
FIFO_RCV_EOP2
O
IOB18
RAM_CS0*
O
FIFO_RD*
B
IOB19
RAM_CS1*
O
FIDO_WR*
B
IOB20
RAM_CS2*
O
FIFO_EMPTY*
B
IOB21
RAM_CS3*
O
FIFO_FULL*
B
IOB22
RAM_TEST
O
ADC:_RDY
I
IOB23
RAM_ TRM_RDY
O
ADC_TRIG
I
IOB24
RAM_RCV_RDY
O
FIFO_TRM_EOP1
I
IOB25
RAM_BUS_REQ*
I
FIFO_TRM_EOP2
I
IOB26
RAM_START_TRM
I
FIFO_RCV_EOP_ACK
I
IOB27
RAM_START_RCV
I
FIFO_TRM_PAR
I
Pin
Mapped to
I/O
Register
GPIO0
RTS1*UART1
O
UART1_CTRL (0x59): D7
GPIO1
CTS1*UART1
I
UART1_CTRL (0x59): D 7
GPIO2
EXT_IREQ0*
I
IFCONF (0x01): D6
GPIO3
EXT_IREQ1*
I
IFCONF (0x01): D 6
GPIO4
TxD2UART2
O
IFCONF (0x01): D7
GPIO5
RxD2UART2
I
IFCONF (0x01): D7
GPIO6
RTS2*UART2
O
UART2_CTRL (0x72): D7
GPIO7
CTS2*UART2
I
UART2_CTRL (0x72): D7
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