參數(shù)資料
型號(hào)： T7630
廠商： Lineage Power
英文描述： Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器)
中文描述： 雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ）（雙個(gè)T1/E1 5.0V短距離通信終端器）
文件頁(yè)數(shù)： 1/210頁(yè)
文件大?。?/td> 3075K
代理商： T7630
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Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Features
The T7630 Dual T1/E1 Terminator consists of two
independent, highly integrated, software-config-
urable, full-featured short-haul transceiver/framers.
The T7630 provides glueless interconnection from a
T1/E1 line to a digital PCM system. Minimal external
clocks are needed. Only a system clock/frame sync
and a phase-locked line rate clock are required. Sys-
tem diagnostic and performance monitoring capabil-
ity with integrated programmable test pattern
generator/detector and loopback modes is provided.
Power Requirements and Package
I
Single 5 V ± 5% supply.
I
Low power: 375 mW per channel maximum.
I
144-pin TQFP package.
I
Operating temperature range: –40 °C to +85 °C.
T1/E1 Line Interface Features
I
Full T1/E1 pulse template compliance.
I
Receiver provides equalization for up to 11 dB of
loss.
I
Digital clock and data recovery.
I
Line coding: B8ZS, HDB3, ZCS, and AMI.
I
Line interface coupling and matching networks for
T1 and E1 (120
and 75
).
T1/E1 Framer Features
I
Supports T1 framing modes ESF, D4, SLC
-96,
T1DM DDS.
I
Supports G.704 basic and CRC-4 multiframe for-
mat E1 framing and procedures consistent with
G.706.
I
Supports unframed transmission format.
I
T1 signaling modes: transparent; ESF 2-state,
4-state, and 16-state; D4 2-state and 4-state;
SLC-96 2-state, 4-state, 9-state and 16-state. E1
signaling modes: transparent and CAS.
I
Alarm reporting and performance monitoring per
AT&T, ANSI*, and ITU-T standards.
I
Programmable, independent transmit and receive
system interfaces at a 2.048 MHz, 4.096 MHz, or
8.192 MHz data rate.
I
System interface master mode for generation of
system frame sync from the line source.
I
Internal phase-locked loop (with external VCXO)
for generation of system clock from the line source.
Facility Data Link Features
I
HDLC or transparent modes.
I
Automatic transmission and detection of ANSI
T1.403 FDL performance report message and bit-
oriented codes.
I
64-byte FIFO in both transmit and receive direc-
tions.
Microprocessor Interface
I
33 MHz, 8-bit data interface, no wait-states.
I
Intel
or Motorola
interface modes with multi-
plexed or demultiplexed buses.
I
Directly addressable control registers.
Applications
I
Customer Premises Equipment—
CSU/DSU,
routers, digital PBX, channel banks (CB), base
transceiver stations (BTS-picocell), small switches,
and digital subscriber loop access multiplexers
(DSLAM).
I
Loop/Access
—DLC/IDLC, DCS, BTS (microcell/
macrocell), DSLAMs, and multiplexers (terminal,
synchronous/asynchronous, add drop).
I
Central Office
—Digital switches, DCS, CB,
access concentrators, remote switch modules
(RSM), and DSLAMs.
I
Test Equipment
—Transmission/BERT tester.
* ANSI is a registered trademark of American National Standards
Institute, Inc.
Intelis a registered trademark of Intel Corporation.
Motorola s a registered trademark of Motorola, Inc.
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