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參數(shù)資料
| 型號： | T68S1MGC-8 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Low Power 1M (128Kx8)-Bits Static RAM |
| 中文描述： | 低功耗100萬（128Kx8）位靜態(tài)存儲器 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 156K |
| 代理商： | T68S1MGC-8 |
2003-REV 090
T68 K/S/R 1M
Speed Bin
-7 (70ns)
-8(85ns)
-10(100ns)
Symbol
Parameter List
Min
Max
Min
Max
Min
Max
Units
t
RC
Read Cycle Time
70
-
85
-
100
-
ns
t
AA
Address Access Time
-
70
-
85
-
100
ns
t
CO
Chip Select to Output
-
70
-
85
-
100
ns
t
OE
Output Enable to Valid Output
-
35
-
40
-
50
ns
t
LZ
Chip Select to Low-Z Output
10
-
10
-
10
-
ns
t
OLZ
Output Enable to Low-Z Output
5
-
5
-
5
-
ns
t
HZ
Chip Disable to High-Z Output
0
25
0
25
0
30
ns
t
OHZ
Output Disable to High-Z Output
0
25
25
30
ns
t
OH
Output Hold From Address
10
-
10
-
15
-
ns
Speed Bin
-7 (70ns)
-8(85ns)
-10 (100ns)
Symbol
Parameter List
Min
Max
Min
Max
Min
Max
Units
t
WC
Write Cycle Time
70
-
85
-
100
-
ns
t
CW
Chip Select to End of Write
60
-
70
-
80
-
ns
t
AS
Address Setup Time
0
-
0
-
0
-
ns
t
AW
Address Valid to End of Write
60
-
70
-
80
-
ns
t
WP
Write Pulse Width
55
-
60
-
70
-
ns
t
WR
Write Recovery Time
0
-
0
-
0
-
ns
t
WHZ
Write to Output High-Z
0
25
0
25
0
30
ns
t
DW
Data to Write Time Overlap
30
-
35
-
40
-
ns
t
DH
Data Hold from Write Time
0
-
0
-
0
-
ns
t
OW
End Write to Output Low-Z
5
-
5
-
5
-
ns
￠
AC ELECTR I CAL CHARACTE RI STI CS
TEST CONDI TI ONS
Input Pulse Level: 0.2Vcc(
V
iL
), 0.8Vcc(
V
IH
Input Rising and Falling Time: 5ns
Input and Output Reference Voltage: 0.9V(R), 1.1V(S), 1.5V (K)
Output Load: C
L
= 30pF + one TTL gate
READ CYCLE
W RI TE CY CLE
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