參數(shù)資料
型號(hào): T6829-T3S
廠商: ATMEL CORP
元件分類: 外設(shè)及接口
英文描述: SIPO BASED PRPHL DRVR, PDSO16
封裝: POWER, SO-16
文件頁(yè)數(shù): 12/16頁(yè)
文件大小: 184K
代理商: T6829-T3S
5
T6819/T6829 [Preliminary]
4531D–BCD–07/04
Table 2. Output Data Protocol
Bit
Output (Status)
Register
Function
0
TP
Temperature prewarning: high = warning
1
Status LS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off); not affected by SRR
2
Status HS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off); not affected by SRR
3
Status LS2
Description see LS1
4
Status HS2
Description see HS1
5
Status LS3
Description see LS1
6
Status HS3
Description see HS1
7
n. u.
Not used
8
n. u.
Not used
9
n. u.
Not used
10
n. u.
Not used
11
n. u.
Not used
12
n. u.
Not used
13
OVL
Over-load detected: set high, when at least one output is switched
off by a short-circuit condition or an overtemperature event. Bits 1
to 6 can be used to detect the affected switch.
(open-load detection bit OLD = high)
14
INH
Inhibit: this bit is controlled by software (bit SI in input register)
High = standby, low = normal operation
15
PSF
Power-supply fail: undervoltage at pin VS detected
After power-on reset, the input register has the following status:
Bit 15
SI
Bit 14
OCS
Bit 13
OLD
Bit 12
PH3
Bit 11
PL3
Bit 10
PH2
Bit 9
PL2
Bit 8
PH1
Bit 7
PL1
Bit 6
HS3
Bit 5
LS3
Bit 4
HS2
Bit 3
LS2
Bit 2
HS1
Bit 1
LS1
Bit 0
SRR
H
L
LL
L
The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during
normal operation.
Bit 15
Bit 14
Bit 13
(OCS)
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3
(LS2)
Bit 2
(HS1)
Bit 1
(LS1)
Bit 0
(SRR)
H
L
LLL
LL
L
H
L
H
L
LL
L
H
L
LL
L
H
L
LL
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