參數(shù)資料
型號(hào): T6816-TIQ
廠商: ATMEL CORP
元件分類: 外設(shè)及接口
英文描述: 40-V Dual Hex Output Driver with Serial Input Control
中文描述: 0.95 A SIPO BASED PRPHL DRVR, PDSO28
封裝: POWER, SO-28
文件頁(yè)數(shù): 4/15頁(yè)
文件大?。?/td> 171K
代理商: T6816-TIQ
4
T6816
4595B–BCD–05/03
Functional Description
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI syn-
chronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0,
SRR) has to be transferred first. Execution of new input data is enabled on the rising
edge of the CS signal. When CS is high, Pin DO is in tri-state condition. This output is
enabled on the falling edge of CS. Output data will change their state with the rising
edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is
transferred first.
Figure 3.
Data Transfer Input Data Protocol
SRR
LS1
HS1
LS2
HS2
LS3
HS3
LS4
HS4
LS5
HS5
LS6
HS6
OLD
SCT
SI
CS
DI
CLK
DO
TP
SLS1
SHS1
SLS2
SHS2
SLS3
SHS3
SLS4
SHS4
SLS5
SHS5
SLS6
SHS6
SCD
INH
PSF
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Table 1.
Input Data Protocol
Bit
Input Register
Function
0
SRR
Status register reset (high = reset; the bits PSF, SCD and
overtemperature shutdown in the output data register are set to
low)
1
LS1
Controls output LS1 (high = switch output LS1 on)
2
HS1
Controls output HS1 (high = switch output HS1 on)
3
LS2
See LS1
4
HS2
See HS1
5
LS3
See LS1
6
HS3
See HS1
7
LS4
See LS1
8
HS4
See HS1
9
LS5
See LS1
10
HS5
See HS1
11
LS6
See LS1
12
HS6
See HS1
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