• 參數(shù)資料
    型號: T5760
    廠商: Atmel Corp.
    英文描述: UHF ASK/FSK Receiver
    中文描述: 超高頻ASK / FSK接收器
    文件頁數(shù): 7/32頁
    文件大小: 765K
    代理商: T5760
    T5761
    T5760 /
    Preliminary Information
    Rev. A2, 19-Oct-00
    7 (32)
    ing bit-check mode, the incoming data stream is analyzed
    bit by bit contra a valid transmitter signal. If no valid
    signal is present, the receiver is set back to sleep mode af-
    ter the period T
    Bit-check
    . This period varies check by
    check as it is a statistical process. An average value for
    T
    Bit-check
    is given in the electrical characteristics. During
    T
    Startup
    and T
    Bit-check
    the current consumption is I
    S
    = I
    Son
    .
    The condition of the receiver is indicated on Pin IC_AC-
    TIVE. The average current consumption in polling mode
    is dependent on the duty cycle of the active mode and can
    be calculated as:
    I
    Spoll
    I
    Soff
    T
    Sleep
    T
    Sleep
    I
    Son
    T
    Startup
    (T
    Startup
    T
    Bitcheck
    )
    T
    Bitcheck
    During T
    Sleep
    and T
    Startup
    the receiver is not sensitive to
    a transmitter signal. To guarantee the reception of a trans-
    mitted command the transmitter must start the telegram
    with an adequate preburst. The required length of the
    preburst depends on the polling parameters T
    Sleep
    ,
    T
    Startup
    , T
    Bit-check
    and the start-up time of a connected
    μ
    C
    (T
    Start,
    μ
    C
    ). Thus, T
    Bit-check
    depends on the actual bit rate
    and the number of bits (N
    Bit-check
    ) to be tested.
    The following formula indicates how to calculate the
    preburst length.
    T
    Preburst
    Sleep Mode
    T
    Sleep
    + T
    Startup
    + T
    Bit-check
    + T
    Start_ C
    The length of period T
    Sleep
    is defined by the 5-bit word
    Sleep of the OPMODE register, the extension factor
    XSleep (according to table 9),
    and the basic clock cycle
    T
    Clk
    . It is calculated to be:
    T
    Sleep
    = Sleep
    X
    Sleep
    1024
    In US- and European applications, the maximum value of
    T
    Sleep
    is about 60 ms if XSleep is set to 1. The time reso-
    lution is about 2 ms in that case. The sleep time can be
    extended to almost half a second by setting XSleep to 8.
    XSleep can be set to 8 by bit XSleep
    Std
    to
    1
    .
    According to table 8, the highest register value of sleep
    sets the receiver into a permanent sleep condition. The re-
    ceiver remains in that condition until another value for
    Sleep is programmed into the OPMODE register. This
    function is desirable where several devices share a single
    data line and may also be used for
    μ
    C polling
    via Pin
    POLLING/_ON, the receiver can be switched on and off.
    T
    Clk
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