參數(shù)資料
型號(hào): T5760-TGQ
廠商: ATMEL CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: UHF ASK/FSK Receiver
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO20
封裝: SO-20
文件頁數(shù): 6/32頁
文件大?。?/td> 765K
代理商: T5760-TGQ
T5760 T5761
/
Rev. A2, 19-Oct-00
Preliminary Information
6 (32)
60
50
40
30
20
10
0
4
3
2
1
0
1
2
3
4
df ( MHz )
d
Figure 6. Narrow band receiving frequency response
100
80
60
40
20
0
12
9
6
3
0
3
6
9
12
df ( MHz )
d
Figure 7. Wide band receiving frequency response
Polling Circuit and Control Logic
The receiver is designed to consume less than 1 mA while
being sensitive to signals from a corresponding trans-
mitter. This is achieved via the polling circuit. This circuit
enables the signal path periodically for a short time.
During this time the bit-check logic verifies the presence
of a valid transmitter signal. Only if a valid signal is
detected the receiver remains active and transfers the data
to the connected
μ
C. If there is no valid signal present the
receiver is in sleep mode most of the time resulting in low
current consumption. This condition is called polling
mode. A connected
μ
C is disabled during that time.
All relevant parameters of the polling logic can be config-
ured by the connected
μ
C. This flexibility enables the
user to meet the specifications in terms of current con-
sumption, system response time, data rate etc.
Regarding the number of connection wires to the C, the
receiver is very flexible. It can be either operated by a
single bi-directional line to save ports to the connected C
or it can be operated by up to five uni-directional ports.
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the
analog filtering is derived from one clock. This clock
cycle T
Clk
is derived from the crystal oscillator (XTO) in
combination with a divide by 14 circuit. According to
chapter
RF Front End
, the frequency of the crystal oscil-
lator (f
XTO
) is defined by the RF input signal (f
RFin
) which
also defines the operating frequency of the local oscillator
(f
LO
). The basic clock cycle is T
Clk
= 14/ f
XTO
giving
T
Clk
= 2.066 s
for
T
Clk
= 1.961 s for f
RF
= 915 MHz
T
Clk
controls the following application-relevant parame-
ters:
f
RF
= 868.3 MHz
and
Timing of the polling circuit including bit check
Timing of the analog and digital signal processing
Timing of the register programming
Frequency of the reset marker
IF filter center frequency (f
IF0
)
Most applications are dominated by two transmission fre-
quencies: f
Transmit
= 915 MHz is mainly used in USA,
f
Transmit
= 868.3 MHz in Europe. In order to ease the
usage of all T
Clk
-dependent parameters on this electrical
characteristics display three conditions for each parame-
ter.
Application USA
(f
XTO
= 7.14063 MHz, T
Clk
= 1.961
μ
s)
Application Europe
(f
XTO
= 6.77617 MHz, T
Clk
= 2.066
μ
s)
Other applications
The electrical characteristic is given as a function of
T
Clk
.
The clock cycle of some function blocks depends on the
selected baud-rate range (BR_Range) which is defined in
the OPMODE register. This clock cycle T
XClk
is defined
by the following formulas for further reference:
BR_Range = BR_Range0: T
XClk
= 8
×
T
Clk
BR_Range1: T
XClk
= 4
×
T
Clk
BR_Range2: T
XClk
= 2
×
T
Clk
BR_Range3: T
XClk
= 1
×
T
Clk
Polling Mode
According to figure 11, the receiver stays in polling mode
in a continuous cycle of three different modes. In sleep
mode the signal processing circuitry is disabled for the
time period T
Sleep
while consuming low current of
I
S
= I
Soff
. During the start-up period, T
Startup
, all signal
processing circuits are enabled and settled. In the follow-
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