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參數(shù)資料
| 型號(hào)： | T436416C-7S |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| 中文描述： | 4米× 16 SDRAM的100萬x 16Bit的X 4Banks同步DRAM |
| 文件頁(yè)數(shù)： | 26/28頁(yè) |
| 文件大?。?/td> | 651K |
| 代理商： | T436416C-7S |
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TE
CH
tm
Self Refresh Entry & Exit Cycle
0
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T436416C
TM Technology Inc. reserves the right
P.26
to change products or specifications without notice.
Publication Date: AUG. 2004
Revision: A
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S elf R efre sh E n try
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A u to R e fresh
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*Note : TO ENTER SELF REFRESH MODE
1.
CS
,RAS &
CAS
with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs inculding the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays ‘Low’.
Cf.) Once the device enters self refresh mode, minimum
t
RAS
is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5.
CS
starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. Burst auto refresh is required before self refresh entry and after self refresh exit if the system uses
burst refresh.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T436416C-7SG | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-5C | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-5CG | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-5S | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T436416C-7SG | 制造商:TMT 制造商全稱:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D | 制造商:TMT 制造商全稱:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-5C | 制造商:TMT 制造商全稱:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-5CG | 制造商:TMT 制造商全稱:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-5S | 制造商:TMT 制造商全稱:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
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