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參數(shù)資料
| 型號(hào)： | T436416A-7.5SG |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 4M X 16 SDRAM |
| 中文描述： | 4米× 16內(nèi)存 |
| 文件頁數(shù)： | 27/29頁 |
| 文件大?。?/td> | 712K |
| 代理商： | T436416A-7.5SG |
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TE
CH
tm
Self Refresh Entry & Exit Cycle
0
1
2
T436416A
TM Technology Inc. reserves the right
P.27
to change products or specifications without notice.
Publication Date: MAY. 2003
Revision: B
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 /A P
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D Q M
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1 0
1 1
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:D o n 't c a re
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* N o te 2
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* N o te 6
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* N o te 5
t
S S
t
R C m in
H i-z
S e lf R e fre s h E n try
S e lf R e fre s h E x it
A u to R e fre sh
H i-z
*Note : TO ENTER SELF REFRESH MODE
1.
CS
,RAS &
CAS
with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs inculding the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays ‘Low’.
Cf.) Once the device enters self refresh mode, minimum
t
RAS
is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5.
CS
starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the
system uses burst refresh.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T436416A-7S | TERMINAL BLOCK END BARRIER IEC +OPTIONS |
| T436416A-7SG | 4M X 16 SDRAM |
| T436416A-8S | 4M X 16 SDRAM |
| T436416A-8SG | 4M X 16 SDRAM |
| T436416C | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T436416A-7S | 制造商:TMT 制造商全稱:TMT 功能描述:4M X 16 SDRAM |
| T436416A-7SG | 制造商:TMT 制造商全稱:TMT 功能描述:4M X 16 SDRAM |
| T436416A-8S | 制造商:TMT 制造商全稱:TMT 功能描述:4M X 16 SDRAM |
| T436416A-8SG | 制造商:TMT 制造商全稱:TMT 功能描述:4M X 16 SDRAM |
| T436416C | 制造商:TMT 制造商全稱:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
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