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參數資料
| 型號： | SYS32512LK-015 |
| 英文描述： | 512 K x 32 Static RAM |
| 中文描述： | 512畝× 32靜態(tài)RAM |
| 文件頁數： | 6/11頁 |
| 文件大?。?/td> | 270K |
| 代理商： | SYS32512LK-015 |
T
Issue 5.0 June 1999
PAGE 6
Address
Data Out
Valid Data
t
RC
t
AA
t
ACS
t
OLZ
t
CLZ(4,5)
t
CHZ(3,4,5)
t
OHZ
t
OH
/CS
/OE
NOTES
(READ CYCLE)
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or
V
levels.
4. At any given temperature and voltage condition, t
CHZ
(Max.) is less than t
CLZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
±
200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with /CS=V
IL
.
7. Address valid prior to coincident with /CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
9. /CS=/CS1~4
t
OE
Previous Data Valid
Data Valid
Address
Data Out
t
RC
t
AA
t
OH
Read Cycle 1
(Address Controlled, /CS=/OE=V
IL
, /WE=V
IH
)
Read Cycle 2
(/WE = V
IH
)
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| SYS32512LKI-010 | 512 K x 32 Static RAM |
| SYS32512LKI-012 | 512 K x 32 Static RAM |
| SYS32512LKI-015 | 512 K x 32 Static RAM |
| SYS32512LKXA-010 | 512 K x 32 Static RAM |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SYS32512LK-020 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 SRAM Module |
| SYS32512LK-025 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 SRAM Module |
| SYS32512LK-30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 SRAM Module |
| SYS32512LK-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 SRAM Module |
| SYS32512LKI-010 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:512 K x 32 Static RAM |
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