Precision Edge SY89876L Micrel, Inc. M9999-082407 hbwhelp@micrel.com or (408) 955-1690 PACKAGE/ORDERI" />
參數(shù)資料
型號(hào): SY89876LMG
廠商: Micrel Inc
文件頁(yè)數(shù): 2/8頁(yè)
文件大?。?/td> 0K
描述: IC CLK BUFF DVDR 1:2 2GHZ 16-MLF
標(biāo)準(zhǔn)包裝: 100
系列: Precision Edge®
類型: 扇出緩沖器(分配),除法器
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
輸入: CML,HSTL,LVDS,LVPECL
輸出: LVDS
頻率 - 最大: 2GHz
電源電壓: 2.97 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤(pán),16-MLF?
供應(yīng)商設(shè)備封裝: 16-MLF?(3x3)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1084 (CN2011-ZH PDF)
其它名稱: 576-2106-5
SY89876LMG-ND
2
Precision Edge
SY89876L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package
Operating
Package
Lead
Part Number
Type
Range
Marking
Finish
SY89876LMI
MLF-16
Industrial
876L
Sn-Pb
SY89876LMITR(2)
MLF-16
Industrial
876L
Sn-Pb
SY89876LMG(3)
MLF-16
Industrial
876L with
Pb-Free
Pb-Free bar-line indicator
NiPdAu
SY89876LMGTR(2, 3)
MLF-16
Industrial
876L with
Pb-Free
Pb-Free bar-line indicator
NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
Pin Number
Pin Name
Pin Function
12, 9
IN, /IN
Differential Input: Internal 50 termination resistors to V
T input. Flexible input accepts any
differential input. See “Input Interface Applications” section.
1, 2, 3, 4
Q0, /Q0
Differential Buffered LVDS Outputs: Divided by 1, 2, 4, 8 or 16. See “Truth Table.”
Q1, /Q1
Unused output pairs must be terminated with 100 across the different pair.
16, 15, 5
S0, S1, S2
Select Pins: See “Truth Table.” LVTTL/CMOS logic levels. Internal 25k pull-up resistor.
Logic HIGH if left unconnected (divided by 16 mode.) Input threshold is VCC/2.
6
NC
No Connect.
8
/RESET,
LVTTL/CMOS Logic Levels: Internal 25k pull-up resistor. Logic HIGH if left unconnected.
/DISABLE
Apply LOW to reset the divider (divided by 2, 4, 8 or 16 mode). Also acts as a disable/enable
function. The reset and disable function occurs on the next high-to-low clock input transition.
Input threshold is VCC/2.
10
VREF-AC
Reference Voltage: Equal to V
CC–1.4V (approx.). Used for AC-coupled applications only.
Decouple the VREF–AC pin with a 0.01F capacitor. See “Input Interface Applications” section.
11
VT
Termination Center-Tap: For CML or LVDS inputs, leave this pin floating. Otherwise, See
Figures 4a to 4f “Input Interface Applications” section.
7, 14
VCC
Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitor.
13
GND, Exposed
Ground. Exposed pad must be connected to the same potential as the GND pin.
pad
PIN DESCRIPTION
13
14
15
16
12
11
10
9
1
2
3
4
8
7
6
5
Q0
/Q0
Q1
/Q1
IN
VT
VREF-AC
/IN
S0
S1
VC
C
GN
D
S2
NC
VCC
/RESET
16-Pin MLF (MLF-16)
/RESET(1)
S2
S1
S0
Outputs
1
0
X
Reference Clock (pass through)
1
0
Reference Clock ÷2
1
0
1
Reference Clock ÷4
1
0
Reference Clock ÷8
1
Reference Clock ÷16
0(1)
X
Q = LOW, /Q = HIGH
Clock Disable
Note:
1. Reset/Disable function is asserted on the next clock input (IN, /IN)
high-to-low transition.
TRUTH TABLE
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