參數(shù)資料
型號(hào): SY89847UMG TR
廠商: Micrel Inc
文件頁(yè)數(shù): 1/10頁(yè)
文件大?。?/td> 0K
描述: IC CLK BUFF MUX 2:5 2GHZ 32-MLF
標(biāo)準(zhǔn)包裝: 1,000
系列: Precision Edge®
類型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 2:5
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,PECL
輸出: LVDS
頻率 - 最大: 2GHz
電源電壓: 2.375 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,32-MLF?
供應(yīng)商設(shè)備封裝: 32-MLF?(5x5)
包裝: 帶卷 (TR)
其它名稱: SY89847UMGTR
SY89847UMGTR-ND
SY89847U
1.5GHz Precision, LVDS 1:5 Fanout with 2:1
MUX and Fail Safe Input with Internal
Termination
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
Oct. 1, 2013
M9999-060107-B
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY89847U is a 2.5V, 1:5 LVDS fanout buffer
with a 2:1 differential input multiplexer (MUX). A
unique Fail-Safe Input (FSI) protection prevents
metastable output conditions when the selected
input clock fails to a DC voltage (voltage between
the pins of the differential input drops significantly
below 100mV).
The differential input includes Micrel’s unique, 3-pin
internal termination architecture that can interface to
any differential signal (AC- or DC-coupled) as small
as 100mV (200mVPP) without any level shifting or
termination resistor networks in the signal path. The
outputs are LVDS compatible with very fast rise/fall
times guaranteed to be less than 210ps.
The SY89847U operates from a 2.5V ±5% supply
and
is
guaranteed
over
the
full
industrial
temperature
range
of
–40°C to +85°C. The
SY89847U is part of Micrel’s high-speed, Precision
Edge
product line.
All support documentation can be found on Mi
crel’s
web site at: www.micrel.com.
Functional Block Diagram
Precision Edge
Features
Selects between two sources, and provides 5
precision LVDS copies
Fail-Safe Input
– Prevents outputs from oscillating when input is
invalid
Guaranteed AC performance over temperature and
supply voltage:
– DC-to >1.5GHz throughput
– <1000ps Propagation Delay (IN-to-Q)
– <210ps Rise/Fall times
Ultra-low jitter design:
– 150fs RMS phase jitter (Typ)
– 0.7ps
RMS MUX crosstalk induced jitter
Unique, patented MUX input isolation design
minimizes adjacent channel crosstalk
Unique, patented internal termination and VT pin
accepts DC- and AC-coupled inputs (CML, PECL,
LVDS)
Wide input voltage range VCC to GND
2.5V ±5% supply voltage
-40°C to +85°C industrial temperature range
Available in 32-pin (5mm x 5mm) QFN package
Applications
Fail-safe clock protection
Ultra-low jitter LVDS clock distribution
Rack-based Telecom/Datacom
Markets
LAN/WAN
Enterprise servers
ATE
Test and measurement
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