參數(shù)資料
型號: SY89834UMITR
廠商: MICREL INC
元件分類: 時鐘及定時
英文描述: 2.5V/3.3V TWO INPUT , 1GHz LVTTL/CMOS-TO-LVPECL 1:4 FANOUT BUFFER/TRANSLATOR
中文描述: 89834 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 4 INVERTED OUTPUT(S), QCC16
封裝: 3 X 3 MM, MLF-16
文件頁數(shù): 2/10頁
文件大?。?/td> 105K
代理商: SY89834UMITR
2
PRELIMINARY
Precision Edge
SY89834U
Micrel
PACKAGE/ORDERING INFORMATION
Ordering Information
Package
Type
MLF-16
MLF-16
Operating
Range
Industrial
Industrial
Package
Marking
834U
834U
Part Number
SY89834UMI
SY89834UMITR*
*Tape and Reel
Pin Number
Pin Name
Pin Function
15, 16
(Q0, /Q0) to
(Q3, /Q3)
LVPECL Differential (Outputs): Terminate to VCC
2V. See
Termination Recommendations
section. Unused outputs may be left floating without impacting jitter and skew.
1, 2, 3, 4, 5, 6
8
EN
TTL/CMOS Compatible Synchronous Enable: When EN goes LOW, Q outputs will go LOW
and /Q outputs will go HIGH on the next LOW transition at IN inputs. Input threshold is
V
CC
/2V. Includes a 25k
pull-up resistor. Default state is HIGH when left floating. The internal
latch is clocked on the falling edge of the input signal (IN1, IN2).
TTL/CMOS Compatible Data/Clock (Inputs): IN1 and IN2 include a 25k
pull-up resistor.
The default state is HIGH when left floating.
9, 12
IN2, IN1
10
NC
No Connect. Not internally connected.
11
SEL
TTL/CMOS Compatible Select Input for signals IN1 and IN2. The input threshold is
V
CC
/2V. HIGH at the SEL input selects signal IN1. LOW at the SEL input selects signal IN2.
SEL includes a 25k
pull-up resistor. The default state is HIGH when left floating.
Ground. Exposed pad internally connected to GND and must be connected to a ground plane
for proper termination.
13,
GND
Exposed Pad
7, 14
VCC
Positive Power Supply: Connect V
CC
pins together on the PCB to maintain the same
potential. Bypass with 0.1
μ
F//0.01
μ
F low ESR capacitors.
PIN DESCRIPTION
1
2
3
4
12
11
10
9
16 15 14 13
5
6
7
8
Q1
/Q1
Q2
/Q2
IN1
SEL
NC
IN2
G
V
Q
/
E
V
/
Q
16-Pin MLF
IN1
IN2
EN
SEL
Q0–Q3
/Q0–Q3
0
X
1
1
0
1
1
X
1
1
1
0
X
0
1
0
0
1
X
1
1
0
1
0
X
X
0
X
0
(1)
0
(1)
Note 1.
On next negative transition of the input signal (IN).
TRUTH TABLE
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