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參數(shù)資料
| 型號(hào)： | SY89827LHY |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CLK FANT BUF MUX TRNSL 64TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | Precision Edge® |
| 類(lèi)型： | 扇出緩沖器（分配），多路復(fù)用器，變換器 |
| 電路數(shù)： | 1 或 2 |
| 比率 - 輸入:輸出： | 4:20，2:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HSTL，LVPECL |
| 輸出： | HSTL |
| 頻率 - 最大： | 500MHz |
| 電源電壓： | 3.3 V ~ 3.47 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 64-EP-TQFP |
| 包裝： | 托盤(pán) |
4
Precision Edge
SY89827L
Micrel, Inc.
M9999-073010
hbwhelp@micrel.com or (408) 955-1690
PIN DESCRIPTIONS
Internal
PinNumber
PinName
I/O
Type
P/U
PinFunction
5, 6
HSTL_CLKA
Input
HSTL
Differential clock input selected by CLK_SEL1, SEL1 and SEL2.
/HSTL_CLKA
Canbeleftfloatingifnotselected.Floatinginput,ifselected
produces an indeterminate output. HSTL input signal requires
externaltermination50-to-GND.
2, 3
HSTL_CLKB
Input
HSTL
Differential clock input selected by CLK_SEL1, SEL1 and SEL2.
/HSTL_CLKB
Canbeleftfloatingifnotselected.Floatinginput,ifselected
produces an indeterminate output. HSTL input signal requires
externaltermination50-to-GND.
8,9
LVPECL_CLKA Input LVPECL
75k
DifferentialclockinputselectedbyCLK_SEL1,SEL1andSEL2.
/LVPECL_CLKA
pull-down Canbeleftfloating.Floatinginput,ifselectedproducesaLOW
at output. Requires external termination. See Figure 1.
12,13
LVPECL_CLKB Input LVPECL
75k
DifferentialclockinputselectedbyCLK_SEL2,SEL1andSEL2.
/LVPECL_CLKB
pull-down Requires external termination. See Figure 1.
7
CLK_SEL1
Input
LVTTL/
11k
SelectsHSTL_CLKAinputwhenLOWandLVPECL_CLKA
CMOS
Pull-up
input when HIGH.
14
CLK_SEL2
Input
LVTTL/
11k
SelectsHSTL_CLKBinputwhenLOWandLVPECL_CLKB
CMOS
Pull-up
input when HIGH.
16
SEL1
Input
LVTTL/
11k
SelectsinputsourceCLKAwhenLOWandCLKB
CMOS
Pull-up
when HIGH for outputs Q0 – Q9 and /Q0 – /Q9.
1
SEL2
Input
LVTTL/
11k
SelectsinputsourceCLKAwhenLOWandCLKB
CMOS
Pull-up
when HIGH for outputs Q10 – Q19 and /Q10 – /Q19.
11
OE1
Input
LVTTL/
11k
Enableinputsynchronizedinternallytopreventglitchingofthe
CMOS
Pull-up
Q0 – Q9 and /Q0 – /Q9 outputs.
15
OE2
Input
LVTTL/
11k
Enableinputsynchronizedinternallytopreventglitchingofthe
CMOS
Pull-up
Q10 – Q19 and /Q10 – /Q19 outputs.
4
VCCI
Power
Core VCC connected to 3.3V supply. Bypass with 0.1F in
parallelwith0.01FlowESRcapacitorsasclosetoVCCpinsas
possible.
17, 32, 33,
VCCO
Power
Output buffer VCC connected to 1.8V nominal supply. All VCCO
40, 41, 48, 49, 64
pins should be connected together on the PCB. Bypass with
0.1F in parallel with 0.01F low ESR capacitors as close to
VCCO pins as possible.
10
GND
Power
Ground.
63, 61, 59, 57, 55
Q0 – Q9
Output
HSTL
Differential clock outputs from CLKA when SEL1 = LOW and
53, 51, 47, 45, 43
fromCLKBwhenSEL1=HIGH.HSTLoutputs(Qand/Q)must
beterminatedwith50-to-GND.Qoutputsarestaticwhen
OE1=LOW.Unusedoutputpairsmaybeleftfloating.
62, 60, 58, 56, 54
/Q0 – /Q9
Output
HSTL
Differential clock outputs (complement) from CLKA when SEL1 =
52, 50, 46, 44, 42
LOW and from CLKB when SEL1 = HIGH. HSTL outputs (Q and
/Q)mustbeterminatedwith50-to-GND./Qoutputsarestatic
HIGH when OE1 = LOW. Unused output pairs may be left
floating.
39, 37, 35, 31, 29
Q10 – Q19
Output
HSTL
Differential outputs from CLKA when SEL2 = LOW and from
27, 25, 23, 21, 19
CLKB when SEL2 = HIGH. HSTL outputs (Q and /Q) must be
terminatedwith50-to-GND.QoutputsarestaticLOWwhen
OE2=LOW.Unusedoutputpairsmaybeleftfloating.
38, 36, 34, 30, 28
/Q10 – /Q19
Output
HSTL
Differentialoutputs(complement)fromCLKAwhenSEL2=LOW
26, 24, 22, 20, 18
and from CLKB when SEL2 = HIGH. HSTL outputs (Q and /Q)
mustbeterminatedwith50-to-GND./QoutputsarestaticHIGH
whenOE2=LOW.Unusedoutputpairsmaybeleftfloating.
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| SY89827LHY TR | 功能描述:時(shí)鐘緩沖器 3.3V Dual 1:20 Diff HSTL Fanout Buffer (I Temp, Lead Free) RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SY89827LHYTR | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:3.3V 500MHz DUAL 1:10 HSTL FANOUT BUFFER/TRANSLATOR WITH 2:1 MUX INPUT |
| SY89828L | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:3.3V 1GHz DUAL 1:10 PRECISION LVDS FANOUT BUFFER/TRANSLATOR WITH 2:1 INPUT MUX |
| SY89828L_08 | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:3.3V 1GHz DUAL 1:10 PRECISION LVDS FANOUT BUFFER/TRANSLATOR WITH 2:1 INPUT MUX |
| SY89828LHG | 功能描述:IC CLK BUF MUX TRNSL 2:10 64TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:Precision Edge® 標(biāo)準(zhǔn)包裝:1 系列:HiPerClockS™ 類(lèi)型:扇出緩沖器（分配），多路復(fù)用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無(wú) 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:- 其它名稱(chēng):800-1923-6 |
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