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參數(shù)資料
| 型號： | SY89531LHZ |
| 廠商： | MICREL INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 622.08 MHz, OTHER CLOCK GENERATOR, PQFP64 |
| 封裝： | LEAD FREE, TQFP-64 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 105K |
| 代理商： | SY89531LHZ |
11
Precision Edge
SY89531L
Micrel, Inc.
M9999-010808
hbwhelp@micrel.com or (408) 955-1690
Power Supply Filtering Techniques
As with any high-speed integrated circuit, power supply
filtering is very important. At a minimum, V
CCA, VCC_Logic,
and all V
CCO pins should be individually connected using a
via to the power supply plane, and separate bypass
capacitors should be used for each pin. To achieve optimal
jitter performance, each power supply pin should use
separate instances of the circuit shown in Figure 4.
*For VCC_Analog,VCC_TTL, VCC1,
use ferrite bead = 200mA, 0.45
DC,
Murata P/N BLM21A1025
*For VCC_OUT use ferrite bead = 3A, 0.025
DC,
Murata, P/N BLM31P005
*Component size: 0805
1
F
22
F
0.01
F
Ferrite Bead*
“Power Supply”
side
“Device”
side
VCC
Pins
Figure 4. Power Supply Filtering
Output Logic Characteristics
See
“Output Termination Recommendations” for
illustrations. In cases where single-ended output is desired,
the designer should terminate the unused complimentary
output in the same manner as the normal output that is
begin used. Unused output pairs can be left floating. Unused
output banks can be switched off by tying the appropriate
FSEL pins to ground. Unused output pairs that are in a
bank that is disabled can be left floating, regardless of output
driver type.
LVPECL operation:
Typical voltage swing is 700mV
PP to 800mVPP into
50
.
Common mode voltage is V
CC–1.3V, typical.
100
termination across the output pair is NOT
recommended for LVPECL.
HSTL operation (Bank B):
Typical voltage swing is 250mV
PP to 450mVPP into
effective 50
.
Thermal Considerations
This part has an exposed die pad for enhanced heat
dissipation. We strongly recommend soldering the exposed
pad to a ground plane. Where this is not possible, we
recommend maintaining at least 500lfpm air flow.
For additional information on exposed-pad characteristics
and implementation details, see Amkor Technology’s write-
up at www.amkor.com.
FSEL_A2(1) (MSB)
FSEL_A1(1)
FSEL_A0(1) (LSB)
Output Divider
0
Output Disable Function, all outputs: Q = LOW, /Q = HIGH
0
1
VCO
÷ 2
0
1
0
VCO
÷ 4
0
1
VCO
÷ 6
1
0
VCO
÷ 8
1
0
1
VCO
÷ 10
1
0
VCO
÷ 12
1
VCO
÷ 18
POST-DIVIDE FREQUENCY SELECT TABLE (FSEL)
Note 1. Same dividers apply to FSEL_B (0:2) and FSEL_C (0:2).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SY89531LHZ TR | 功能描述:時鐘合成器/抖動清除器 3.3V Programmable HSTL/LVPECL Synthesizer (Green) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SY89531LHZTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND |
| SY89532L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND HSTL BUS CLOCK SYNTHESIZER |
| SY89532L_08 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND LVDS BUS CLOCK SYNTHESIZER |
| SY89532LHC | 功能描述:IC SYNTHESIZR LVPECL/LVDS 64TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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