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參數(shù)資料
| 型號： | SY89482LMG |
| 廠商： | MICREL INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CLOCK DRIVER, QCC24 |
| 封裝： | 4 X 4 MM, LEAD FREE, MLF-24 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 425K |
| 代理商： | SY89482LMG |
Micrel, Inc.
SY89482L
April 2008
4
M9999-040808-A
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
1
VT
Input Termination Center-Tap: Each side of the differential input pair terminates to VT pin.
This pin provides a center-tap to a termination network for maximum interface flexibility. See
“Input Interface Applications” subsection.
2
VREF-AC
Reference Output Voltage: This output biases to VDD-1.4V. It is used when AC-coupling the
inputs (IN, /IN). Connect VREF-AC directly to the VT pin. Bypass with 0.01uF low ESR
capacitors to VDD. Maximum current source or sink is ±0.5mA. See “Input Interface
Applications” subsection.
3, 4
REFIN,
/REFIN
Differential Input Pair: This input pair is the differential signal input to the device. Input
accepts AC- or DC-coupled differential signals as small as 100mV (200mVpp). Each pin of
this pair internally terminates with 50
to the VT pin. See Figure 2a.
12
/EN
Single-ended Input: This TTL/CMOS input disables and enables the output. It has an internal
pull-down and will default to a logic LOW state if left open. When HIGH, the output is forced
into the disable state (Q = LOW and /Q = HIGH). The pull-down current is typically 0.5A.
6, 13
GND,
Exposed Pad
Ground: These are the ground pins for core and input stage. Exposed pad must be
connected to a ground plane that is the same potential as the ground pin.
9, 10
CLKOUT,
/CLKOUT
CML Differential Output Pair: Differential buffered output copy of the input signal with very
low jitter. The output swing is typically 400mV. The output pair is referenced to VDDO. Output
pair can be terminated 100
across or 50 to VBIAS. See “CML Output Termination”
subsection. See Figure 2b.
7
GNDO
Ground: This is the ground pin for output stage. GNDO and GND must be connected
together on the PCB.
8, 11
VDDO
CML Output Driver Power Pins: VDDO enables the output stage to operate from a lower
supply voltage than the core synthesizer voltage. These outputs can be powered from 1.8V
±5% to 3.3V ±10% power supply. For applications that only require 3.3V reference output
operation, VDDO and VDD pins may be connected to a common power supply. Connect both
VDDO pins to same power supply. Bypass with 0.1uF//0.01uF low ESR capacitors as close
to the VDD pins as possible.
15
RESET
Single-ended Input: Reset is active on the Low-to-High edge of the input pulse. It has an
internal pull-down and will default to a logic LOW state if left open. Resetting the part starts
an auto-tune sequence to provide output frequency closest to input frequency. Calibration
setting is lost on power down. The pull-down current is typically 0.5A.
14
LOL
Single-ended Output: This LVTTL/CMOS output asserts HIGH when the PLL is out of phase
lock. LOL is asserted if the PLL frequency deviates more than ±1000ppm for more than 5ms.
This prevents false triggering. The Loss of Lock pin can be directly connected to /EN.
20, 21
FILTERN,
FILTERP
Analog Input: These pins provide reference for PLL loop filter. Connect a LOW ESR capacitor
across these pins as close to the device as possible, clear from any supply lines or adjacent
signal lines. See “External Loop Filter Considerations” for loop filter values. Loop filter
capacitor value depends on I/O frequency selection. Loop filter capacitor layout should
include a quiet ground plane under the loop filter capacitor and loop filter (FILTERP,
FILTERN) pins. Recommend 1206, X5R, 6.3V ceramic type, +/-30%. See “PLL Loop Filter
Capacitor Table”.
18, 23
GNDA
Ground: This is an analog ground pin for the PLL. Connect to “quiet” ground. It is internally
referenced to the VCO. GNDA and Ground must be shorted on the PCB.
19, 22
VDDA
Analog Power: Connect to “quiet” 3.3V ±10% power supply. These pins are not internally
connected and must be shorted on the PCB. VDDA internally connects to the VCO. Bypass
with 0.1F//0.01F low ESR capacitors as close to the pin as possible
16, 17
BW0, BW1
Single-ended Input: These LVTTL/CMOS inputs determine the loop bandwidth of the jitter
reducing PLL. BWSEL0 and BWSEL1 will default to a logic HIGH state if left open with a
typical pull-up current of 1.3A. See “Loop Bandwidth Table.”
5, 24
VDDC
Positive Power Supply: VDDC pins are connected to core and input stage that connects to a
3.3V ±10% power supply. Bypass with 0.1F//0.01F low ESR capacitors as close to the VCC
pins as possible.
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