參數(shù)資料
型號: SY89218UHY
廠商: Micrel Inc
文件頁數(shù): 1/9頁
文件大小: 0K
描述: IC CLK BUFF DVDR MUX 2:15 64TQFP
標(biāo)準(zhǔn)包裝: 160
系列: Precision Edge®
類型: 扇出緩沖器(分配),除法器,多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 2:15
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,PECL
輸出: LVDS
頻率 - 最大: 2GHz
電源電壓: 2.375 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-EP-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 1083 (CN2011-ZH PDF)
其它名稱: 576-1615
SY89218U
Precision 1:15 LVDS Fanout Buffer with 2:1
MUX and Four ÷1/÷2/÷4 Clock Divider Output
Banks
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
August 2007
M9999-082407-C
hbwhelp@micrel.com or (408) 955-1690
General Description
The
SY89218U
is
a
2.5V
precision,
high-speed,
integrated clock divider and LVDS fanout buffer capable
of handling clocks up to 1.5GHz. Optimized for
communications applications, the four independently
controlled output banks are phase-matched and can be
configured for pass through (÷1), ÷2 or ÷4 divider ratios.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that allows the user to
interface to any differential signal (AC- or DC-coupled)
as small as 100mV (200mVPP) without any level shifting
or termination resistor networks in the signal path. The
low-skew, low-jitter outputs are LVDS compatible with
extremely fast rise/fall times guaranteed to be less than
200ps.
The /MR (master reset) input asynchronously resets the
outputs. A four-clock delay after de-asserting /MR allows
the counters to synchronize and start the outputs from
the same state without any runt pulse.
The SY89218U is part of Micrel’s Precision Edge
product family. All support documentation can be found
at Micrel's web site at: www.micrel.com.
Features
Low-skew LVDS output banks with independently
programmable ÷1, ÷2 and ÷4 divider options
Four output banks, 15 total outputs
Guaranteed AC performance over temperature and
voltage:
– Accepts a clock frequency up to 1.5GHz
– <1600ps IN-to-OUT propagation delay
– <200ps rise/fall time
– <35ps within bank skew
Fail Safe Input
– Prevents outputs from oscillating
Ultra-low jitter design:
– <1psRMS random jitter
– <10psPP total jitter (clock)
Patent-pending input termination and VT pin accepts
DC- and AC-coupled inputs (CML, PECL, LVDS)
LVDS-compatible outputs
CMOS/TTL-compatible output enable (EN) and
divider select control
2.5V ±5% power supply
–40°C to +85°C temperature range
Available in 64-pin TQFP
Applications
All SONET/SDH applications
All Fibre Channel applications
All Gigabit Ethernet applications
Markets
LAN/WAN routers/switches
Storage
ATE
Test and measurement
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