- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385892 > SY87701ALZI (MICREL INC) 3.3V 28Mbps to 1.3Gbps AnyRate Clock and Data Recovery PDF資料下載
參數(shù)資料
| 型號(hào)： | SY87701ALZI |
| 廠商： | MICREL INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 3.3V 28Mbps to 1.3Gbps AnyRate Clock and Data Recovery |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁(yè)數(shù)： | 3/15頁(yè) |
| 文件大?。?/td> | 168K |
| 代理商： | SY87701ALZI |
第1頁(yè)第2頁(yè)當(dāng)前第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)
SY87701AL
3
Micrel, Inc.
M9999-111506
hbwhelp@micrel.com or (408) 955-1690
Pin Number
SOIC
4
5
Pin Number
TQFP
2
3
Pin Name
RDINP
RDINN
Pin Function
Serial Data Input (Differential PECL): These built-in line receiver inputs are
connected to the differential receive serial data stream. An internal receive PLL
recovers the embedded clock (RCLK) and data (RDOUT) information. The
incoming data rate can be within one of eight frequency ranges depending on the
state of the FREQSEL pins. See “Frequency Selection” table.
Reference Clock (TTL Inputs): This input is used as the reference for the internal
frequency synthesizer and the “training” frequency for the receiver PLL to keep it
centered in the absence of data coming in on the RDIN inputs.
Carrier Detect (PECL Input): This input controls the recovery function of the
Receive PLL and can be driven by the carrier detect output of optical modules or
from external transition detection circuitry. When this input is HIGH the input data
stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW
the data on the inputs RDIN will be internally forced to a constant LOW, the data
outputs RDOUT will remain LOW, the Link Fault Indicator output LFIN forced LOW
and the clock recovery PLL forced to look onto the clock frequency generated from
REFCLK.
Frequency Select (TTL Inputs): These inputs select the output clock frequency
range as shown in the “Frequency Selection” table.
7
5
REFCLK
27
26
CD
6
8
9
3
26
4
6
7
32
25
FREQSEL1
FREQSEL2
FREQSEL3
DIVSEL1
DIVSEL2
Divider Select (TTL Inputs): These inputs select the ratio between the output clock
frequency (RCLK/TCLK) and the REFCLK input frequency as shown in the
“Reference Frequency Selection” table.
Clock Select (TTL Inputs): This input is used to select either the recovered clock
of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer
(CLKSEL = LOW) to the TCLK outputs.
Link Fault Indicator (TTL Output): This output indicates the status of the input data
stream RDIN. Active HIGH signal is indicating when the internal clock recovery
PLL has locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH
and RDIN is within the frequency range of the Receive PLL (1000ppm).
Receive Data Output (Differential PECL): These ECL 100k outputs represent the
recovered data from the input data stream (RDIN). This recovered data is specified
against the rising edge of RCLK. These outputs must be terminated with 50
to
V
CC
–2 or equivalent. Thhis applies even if these outputs are not used.
Clock Output (Differential PECL): These ECL 100k outputs represent the
recovered clock used to sample the recovered data (RDOUT).
Clock Output (Differential PECL): These ECL 100k outputs represent either the
recovered clock (CLKSEL = HIGH) used to sample the recovered data (RDOUT) or
the transmit clock of the frequency synthesizer (CLKSEL = LOW). These outputs
must be terminated with 50
toV
CC
–2 or equivalent. This applies even if these
outputs are not used.
Clock Synthesis PLL Loop Filter. External loop filter pins for the clock synthesis
PLL.
Clock Recovery PLL Loop Filter. External loop filter pins for the receiver PLL.
17
16
CLKSEL
2
31
LFIN
25
24
24
23
RDOUTP
RDOUTN
22
21
19
18
21
20
18
17
RCLKP
RCLKN
TCLKP
TCLKN
11
12
16
15
28
1
9
10
15
14
PLLSP
PLLSN
PLLRP
PLLRN
V
CC
V
CCA
V
CCO
GND
NC
27, 28,
29, 30
19, 22
12, 13
1, 8
Supply Voltage
(1)
Analog Supply Voltage
(1)
Output Supply Voltage
(1)
Ground
No Connect
20, 23
13, 14
10
13
11
GNDA
Analog Ground
Note:
1. V
CC
, V
CCA
, V
CCO
must be the same value.
PIN DESCRIPTIONS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SY87701ALHG | 3.3V 28Mbps to 1.3Gbps AnyRate Clock and Data Recovery |
| SY87701ALHI | 3.3V 28Mbps to 1.3Gbps AnyRate Clock and Data Recovery |
| SY87701LHG | 3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY |
| SY87701LHGTR | 3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY |
| SY87701LHITR | 3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY87701L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY Use lower-power SY87701AL for new designs |
| SY87701L_06 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY |
| SY87701L_11 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY Use lower-power SY87701AL for new designs |
| SY87701LGI | 制造商:Micrel Inc 功能描述: |
| SY87701LHG | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 3.3V Any-Rate 32-1250 Mbps CDR (I Temp, Green/32 Pin EP-TQFP/Bulk) RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。