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參數(shù)資料
| 型號(hào)： | SY87700LZGTR |
| 廠商： | MICREL INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, LEAD FREE, SOIC-28 |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大?。?/td> | 580K |
| 代理商： | SY87700LZGTR |
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SY87700L
3
Micrel, Inc.
M9999-111406
hbwhelp@micrel.com or (408) 955-1690
Pin Number
SOIC
4
5
Pin Number
TQFP
2
3
Pin Name
RDINP,
RDINN
Pin Function
Serial Data Input (Differential PECL): These built-in line receiver inputs are
connected to the differential receive serial data stream. An internal receive
PLL recovers the embedded clock (RCLK) and data (RDOUT) information.
The incoming data rate can be within one of five frequency ranges depend-
ing on the state of the FREQSEL pins. See “Frequency Selection” table.
Reference Clock (TTL Inputs): This input is used as the reference for the
internal frequency synthesizer and the “training” frequency for the receiver
PLL to keep it centered in the absence of data coming in on the RDIN inputs.
Carrier Detect (PECL Input): This input controls the recovery function of the
Receive PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When this input is
HIGH the input data stream (RDIN) is recovered normally by the Receive
PLL. When this input is LOW the data on the inputs RDIN will be internally
forced to a constant LOW, the data outputs RDOUT will remain LOW, the
Link Fault Indicator output LFIN forced LOW and the clock recovery PLL
forced to look onto the clock frequency generated from REFCLK.
Frequency Select (TTL Inputs): These inputs select the output clock
frequency range as shown in the “Frequency Selection” table.
7
5
REFCLK
27
26
CD
6
8
9
3
26
4
6
7
32
25
FREQSEL1,
FREQSEL2,
FREQSEL3
DIVSEL1,
DIVSEL2
Divider Select (TTL Inputs): These inputs select the ratio between the
output clock frequency (RCLK/TCLK) and the REFCLK input frequency as
shown in the “Reference Frequency Selection” table.
Clock Select (TTL Inputs): This input is used to select either the recovered
clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency
synthesizer (CLKSEL = LOW) to the TCLK outputs.
Link Fault Indicator (TTL Output): This output indicates the status of the
input data stream RDIN. Active HIGH signal is indicating when the internal
clock recovery PLL has locked onto the incoming data stream. LFIN will go
HIGH if CD is HIGH and RDIN is within the frequency range of the Receive
PLL (1000ppm). LFIN is an asynchronous output.
Receive Data Output (Differential PECL): These ECL 100k outputs
represent the recovered data from the input data stream (RDIN). This
recovered data is specified against the rising edge of RCLK.
Clock Output (Differential PECL): These ECL 100k outputs represent the
recovered clock used to sample the recovered data (RDOUT).
Clock Output (Differential PECL): These ECL 100k outputs represent
either the recovered clock (CLKSEL = HIGH) used to sample the recovered
data (RDOUT) or the transmit clock of the frequency synthesizer
(CLKSEL = LOW).
Clock Synthesis PLL Loop Filter. External loop filter pins for the clock
synthesis PLL.
Clock Recovery PLL Loop Filter. External loop filter pins for the receiver
PLL.
Supply Voltage
(1)
Analog Supply Voltage
(1)
Output Supply Voltage
(1)
Ground
No Connect
17
16
CLKSEL
2
31
LFIN
25
24
24
23
RDOUTP,
RDOUTN
22
21
19
18
21
20
18
17
RCLKP,
RCLKN
TCLKP,
TCLKN
11
12
16
15
9
10
15
14
PLLSP,
PLLSN
PLLRP,
PLLRN
V
CC
V
CCA
V
CCO
GND
NC
27, 28,
29, 30
19, 22
12, 13
1, 8
1
20, 23
13, 14
10
Note:
1. V
CC
, V
CCA
, V
CCO
must be the same value.
PIN DESCRIPTIONS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SY87700LZITR | 3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY |
| SY87700VHCTR | 5V/3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY |
| SY87700VHH | 5V/3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY |
| SY87700VHHTR | 5V/3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY |
| SY87700VZCTR | 5V/3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY87700LZI | 功能描述:IC CLOCK/DATA RECOVERY 28-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:AnyRate® 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| SY87700LZITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY |
| SY87700V | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:5V/3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY |
| SY87700V_06 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:5V/3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY |
| SY87700V_08 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:5V/3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY |
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