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參數(shù)資料
| 型號(hào)： | SY87700LHI |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32-TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | AnyRate® |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，ATM 應(yīng)用 |
| 輸入： | PECL |
| 輸出： | PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 175Mbps |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-EPAD-TQFP |
| 包裝： | 托盤 |
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SY87700L
3
Micrel, Inc.
M9999-111406
hbwhelp@micrel.com or (408) 955-1690
Pin Number
SOIC
TQFP
Pin Name
Pin Function
42
RDINP,
Serial Data Input (Differential PECL): These built-in line receiver inputs are
53
RDINN
connected to the differential receive serial data stream. An internal receive
PLL recovers the embedded clock (RCLK) and data (RDOUT) information.
The incoming data rate can be within one of five frequency ranges depend-
ing on the state of the FREQSEL pins. See “Frequency Selection” table.
75
REFCLK
Reference Clock (TTL Inputs): This input is used as the reference for the
internal frequency synthesizer and the “training” frequency for the receiver
PLL to keep it centered in the absence of data coming in on the RDIN inputs.
27
26
CD
Carrier Detect (PECL Input): This input controls the recovery function of the
Receive PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When this input is
HIGH the input data stream (RDIN) is recovered normally by the Receive
PLL. When this input is LOW the data on the inputs RDIN will be internally
forced to a constant LOW, the data outputs RDOUT will remain LOW, the
Link Fault Indicator output LFIN forced LOW and the clock recovery PLL
forced to look onto the clock frequency generated from REFCLK.
64
FREQSEL1,
Frequency Select (TTL Inputs): These inputs select the output clock
86
FREQSEL2,
frequency range as shown in the “Frequency Selection” table.
97
FREQSEL3
332
DIVSEL1,
Divider Select (TTL Inputs): These inputs select the ratio between the
26
25
DIVSEL2
output clock frequency (RCLK/TCLK) and the REFCLK input frequency as
shown in the “Reference Frequency Selection” table.
17
16
CLKSEL
Clock Select (TTL Inputs): This input is used to select either the recovered
clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency
synthesizer (CLKSEL = LOW) to the TCLK outputs.
231
LFIN
Link Fault Indicator (TTL Output): This output indicates the status of the
input data stream RDIN. Active HIGH signal is indicating when the internal
clock recovery PLL has locked onto the incoming data stream. LFIN will go
HIGH if CD is HIGH and RDIN is within the frequency range of the Receive
PLL (1000ppm). LFIN is an asynchronous output.
25
24
RDOUTP,
Receive Data Output (Differential PECL): These ECL 100k outputs
24
23
RDOUTN
represent the recovered data from the input data stream (RDIN). This
recovered data is specified against the rising edge of RCLK.
22
21
RCLKP,
Clock Output (Differential PECL): These ECL 100k outputs represent the
21
20
RCLKN
recovered clock used to sample the recovered data (RDOUT).
19
18
TCLKP,
Clock Output (Differential PECL): These ECL 100k outputs represent
18
17
TCLKN
either the recovered clock (CLKSEL = HIGH) used to sample the recovered
data (RDOUT) or the transmit clock of the frequency synthesizer
(CLKSEL = LOW).
11
9
PLLSP,
Clock Synthesis PLL Loop Filter. External loop filter pins for the clock
12
10
PLLSN
synthesis PLL.
16
15
PLLRP,
Clock Recovery PLL Loop Filter. External loop filter pins for the receiver
15
14
PLLRN
PLL.
27, 28,
VCC
Supply Voltage(1)
1
29, 30
VCCA
Analog Supply Voltage(1)
20, 23
19, 22
VCCO
Output Supply Voltage(1)
13, 14
12, 13
GND
Ground
10
1, 8
NC
No Connect
Note:
1. V
CC, VCCA, VCCO must be the same value.
PIN DESCRIPTIONS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY87700LHITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY Use lower-power SY87700AL for new designs |
| SY87700LSI | 功能描述:IC CLOCK/DATA RECOVERY 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:AnyRate® 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| SY87700LZG | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 3.3V 32Mbps-175Mbps CDR (I Temp, Green/28 SOIC/bulk) RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SY87700LZG TR | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 3.3V 32Mbps-175Mbps CDR (I Temp, Green/28 SOIC/T+R) RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SY87700LZGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY Use lower-power SY87700AL for new designs |
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