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    參數(shù)資料
    

    


    


    
型號(hào)：
SY69952ZH TR

    

    
廠商：
Micrel Inc

    

    
文件頁(yè)數(shù)：
3/8頁(yè)

    

    
文件大小：
0K

    

    
描述：
IC TXRX CLOCK RECOVERY 28-SOIC

    

    
標(biāo)準(zhǔn)包裝：
1,000

    

    
類型：
時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器
    		

    

    
PLL：
是
    		

    

    
主要目的：
以太網(wǎng)，SONET/SDH，ATM 應(yīng)用
    		

    

    
輸入：
PECL
    		

    

    
輸出：
PECL
    		

    

    
電路數(shù)：
1
    		

    

    
比率 - 輸入:輸出：
1:3
    		

    

    
差分 - 輸入:輸出：
是/是
    		

    

    
頻率 - 最大：
155.52Mbps
    		

    

    
電源電壓：
4.75 V ~ 5.25 V
    		

    

    
工作溫度：
0°C ~ 85°C
    		

    

    
安裝類型：
表面貼裝
    		

    

    
封裝/外殼：
28-SOIC（0.295"，7.50mm 寬）
    		

    

    
供應(yīng)商設(shè)備封裝：
28-SOIC
    		

    

    
包裝：
帶卷 (TR)
    		

    

    
其它名稱：
SY69952ZHTR
    SY69952ZHTR-ND
    		

    

    

    

	
    
    
    

    
    
	
    SY69952
    3
    Micrel, Inc.
    M9999-062805
    hbwhelp@micrel.com or (408) 955-1690
    RSER± – Differential PECL Output
    Recovered Serial Data. These Positive ECL 100K outputs
    (+5V referenced) represent the recovered data from the
    input data stream (RIN±). This recovered data is aligned
    with the recovered clock (RCLK±) with a sampling window
    compatible with most data processing devices.
    RCLK± – Differential PECL Output
    Recovered Clock. These Positive ECL 100K outputs (+5V
    referenced) represent the recovered clock from the input
    data stream (RIN±). This recovered clock is used to sample
    the recovered data (RSER±) and has timing compatible
    with most data processing devices.
    LFI – TTL Output
    Link Fault Indicator. This input indicates the status of the
    input data stream (RIN±). It is controlled by three functions;
    the Carrier Detect (CD) input, the internal Transition Detector,
    and the Out of Lock (OOL) detector. The Transition Detector
    determines if RIN± contains enough transitions to be
    accurately recovered by the Receive PLL. The Out of Lock
    detector determines if RIN± is within the frequency range of
    the Receive PLL. When CD is HIGH and RIN± has sufficient
    transitions and is within the frequency range of the Receive
    PLL, the LFI input will be high. If CD is at an ECL LOW or
    RIN± does not contain sufficient transitions or RIN± is outside
    the frequency range of the Receive PLL then the LFI output
    will be LOW. If CD is at a TTL LOW then the LFI output will
    only transition LOW when the frequency of RIN± is outside
    the range of the Receive PLL.
    TOUT± – Differential PECL Output
    Transmit Output. These Positive ECL 100K outputs (+5V
    referenced) represent the buffered version of the Transmit
    data stream (TSER±). This Transmit path is used to take
    weak input signals and rebuffer them to drive low impedance
    copper media.
    TCLK± – Differential PECL Output
    Transmit Clock. These Positive ECL 100K outputs (+5V
    referenced) provide the bit rate frequency source for external
    Transmit data processing devices. This output is synthesized
    by the Transmit PLL and is derived by multiplying the
    REFCLK frequency by eight.
    LOOP – TTL Input
    Loop Back Select. This input is used to select the input
    data stream source that the Receive PLL used for clock
    and data recovery. When the LOOP input is HIGH, the
    Receive input data stream (RIN±) is used for clock and
    data recovery. When LOOP is LOW, the Transmit input
    data stream (TSER±) is used by the Receive PLL for clock
    and data recovery.
    INPUTS
    RIN± – Differential PECL Input
    Receive Input. These built-in line receiver inputs are
    connected to the differential Receive serial input data stream.
    An internal Receive PLL recovers the embedded clock
    (RCLK±) and data (RSER±) information. The incoming data
    rate can be within one of two frequency ranges depending
    on the state of the MODE pin.
    CD – PECL/TTL Input
    Carrier Detect. This input controls the recovery function
    of the Receive PLL and can be driven by the carrier detect
    output from optical modules or from external transition
    detection circuitry. When this input is at an ECL HIGH, the
    input data stream (RIN±) is recovered normally by the
    Receive PLL. When this input is at an ECL LOW, the
    Receive PLL no longer aligns to RIN±, but instead aligns
    with the REFCLKx8 frequency. Also, the Link Fault Indicator
    (LFI) will transition LOW, and the recovered data outputs
    (RSER) will remain LOW regardless of the signal level on
    the Receive data stream inputs (RIN). When the CD input
    is at a TTL LOW (-0.8V), the internal transition detection
    circuitry is disabled.
    TSER± – Differential PECL Input
    Transmit Serial Data. These built-in line receiver inputs
    are connected to the differential Transmit serial input data
    stream. These inputs can receive very low amplitude signals
    and are compatible with all PECL signal levels.
    REFCLK± – Differential PECL/TTL Input
    Reference Clock. This input is the clock frequency
    reference for the clock and data recovery Receive PLL.
    REFCLK is multiplied internally by eight and sets the
    approximate center frequency for the internal Receive PLL
    to track the incoming bit stream. This input is also multiplied
    by eight by the frequency multiplier Transmit PLL to produce
    the bit rate Transmit Clock (TCLK±). REFCLK can be
    connected to either a differential PECL or single-ended TTL
    frequency source. When either REFCLK+ or REFCLK- is at
    a TTL LOW, the opposite REFCLK signal becomes a TTL
    level input.
    OUTPUTS
    ROUT± – Differential PECL Output
    Receive Output. These Positive ECL 100K outputs (+5V
    referenced) represent the buffered version of the input data
    stream (RIN±). This output pair can be used for Receiver
    input data equalization in copper based systems, reducing
    the system impact of data dependent jitter. All PECL outputs
    can be powered down by connecting both outputs to VCC
    or leaving them both unconnected.
    PIN DESCRIPTIONS
    
    
    
    
    
    


    


    

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