參數(shù)資料
型號: SY69952ZC
廠商: Micrel Inc
文件頁數(shù): 4/8頁
文件大?。?/td> 0K
描述: IC TXRX CLOCK RECOVERY 28-SOIC
標(biāo)準(zhǔn)包裝: 27
類型: 時鐘和數(shù)據(jù)恢復(fù)(CDR),多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,ATM 應(yīng)用
輸入: PECL
輸出: PECL
電路數(shù): 1
比率 - 輸入:輸出: 1:3
差分 - 輸入:輸出: 是/是
頻率 - 最大: 155.52Mbps
電源電壓: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC
包裝: 管件
SY69952
4
Micrel, Inc.
M9999-062805
hbwhelp@micrel.com or (408) 955-1690
MODE – 3 Level Input
Frequency Mode Select. This three-level input selects
the frequency range for the clock and data recovery receive
PLL and the frequency multiplier transmit PLL. When the
input is held PECL HIGH (VCC –0.9 typ.), the two PLLs
operate at the SONET (SDH) STS-3 (STM-1) line rate of
155.52MHz. When this input is held TTL LOW (connected
to GND), the two PLLs operate at one SONET STS-1 line
rate of 51.84MHz. The REFCLK± frequency in both operating
modes is 1/8 of the operating frequency. When the MODE
input is ECL LOW (VCC – 1.7 typ), the device enters into
test mode, the TSER± inputs substitue for the internal PLL
VCO for use in factory testing.
PIN DESCRIPTIONS
DESCRIPTION
General
The SY69952 Serial SONET/SDH Transceiver is used in
SONET/SDH and ATM applications to recover clock and
data information from a 155.52MHz or 51.84MHz NRZ (Non
Return to Zero) or NRZI (Non Return to Zero Invert on
ones) serial data stream. This device also provides a bit-
rate Transmit clock, from a byte rate source through the
use of a frequency multiplier PLL, and differential data
buffering for the Transmit side of the system. This device is
compliant with all relevant SONET/SDH specifications
including ANSI T1X1.6/91-022, ANSI T1X1.3/93-006R1 Draft
and ITU/CCITT G958.
Operating Frequency
The SY69952 operates at either of two frequency ranges.
The MODE input selects which of the two frequency ranges
the Transmit frequency multiplier PLL and the Receive clock
and data recovery PLL will operate. When MODE is
connected to VCC, the highest operating range of the device
is selected. A 19.44MHz ± 1% source must drive the
REFCLK input and the two PLLs will multiply this rate by 8
to provide output clocks that operate at 155.52MHz ± 1%.
When the MODE input is connected to ground (GND), the
lowest operating range of the device is selected. A 6.48MHz
± 1% source must drive the REFCLK inputs and the two
PLLs will multiply this rate by 8 to provide output clocks that
operate at 51.84MHz ± 1%.
Transmit Functions
The transmit section of the SY69952 contains a PLL that
takes a REFCLK input and multiplies it by 8 (REFCLKx8) to
produce a PECL (Positive ECL) differential output clock
(TCLK±). The transmitter has two operating ranges that are
selectable with the three-level MODE pin as explained
above. The SY69952 Transmit frequency multiplier PLL
allows low-cost byte rate clock sources to be used to time
the upstream serial data transmitter.
The REFCLK± input can be configured three ways. When
both REFCLK+ and REFCLK- are connected to a differential
100K-compatible PECL source, the REFCLK input will
behave as a differential PECL input. When either the
REFCLK+ or the REFCLK- input is at a TTL LOW, the
other REFCLK input becomes a TTL-level input allowing it
to be connected to a low-cost TTL crystal oscillator. The
REFCLK input structure, therefore, can be used as a
differential PECL input, a single TTL input, or as a dual TTL
clock multiplexing input.
Figure 1. Suggested Loop Filter Values
PLL1±, PLL2± – Loop Filter Inputs
These pins are used to connect the external loop filters
for the two on-board PLLs. See below:
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