參數(shù)資料
型號(hào): SY69753LHI
廠商: MICREL INC
元件分類: 數(shù)字傳輸電路
英文描述: 3.3V 125 MBPS 155 MBPS CLOCK AND DATA RECOVERY
中文描述: CLOCK RECOVERY CIRCUIT, PQFP32
封裝: TQFP-32
文件頁數(shù): 1/9頁
文件大?。?/td> 86K
代理商: SY69753LHI
1
SY69753L
Micrel
3.3V, 125Mbps 155Mbps
CLOCK and DATA RECOVERY
SY69753L
Rev.: B
Issue Date:
Amendment: /2
September 2003
DESCRIPTION
FEATURES
I
Industrial temperature range (–40
°
C to +85
°
C)
I
3.3V power supply
I
SONET/SDH/ATM compatible
I
Clock and data recovery for 125Mbps/155Mbps NRZ
data stream
I
Two on-chip PLLs: one for clock generation and
another for clock recovery
I
Selectable reference frequencies
I
Differential PECL high-speed serial I/O
I
Line receiver input: no external buffering needed
I
Link fault indication
I
100k ECL compatible I/O
I
Complies with Bellcore, ITU/CCITT and ANSI
specifications for OC-3 applications
I
Available in 32-pin EPAD-TQFP
The SY69753L is a complete Clock Recovery and Data
Retiming integrated circuit for OC-3/STS-3 applications
at 155Mbps NRZ. The device is ideally suited for SONET/
SDH/ATM applications and other high-speed data
transmission systems.
Clock recovery and data retiming is performed by
synchronizing the on-chip VCO directly to the incoming
data stream. The VCO center frequency is controlled by
the reference clock frequency and the selected divide
ratio. On-chip clock generation is performed through the
use of a frequency multiplier PLL with a byte rate source
as reference.
The SY69753L also includes a link fault detection
circuit.
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
APPLICATIONS
I
Ethernet media converter
I
SONET/SDH/ATM OC-3
I
Proprietary architectures at 135Mbps to 180Mbps
BLOCK DIAGRAM
PHASE
DETECTOR
FRPHASE/
DETECTOR
CPUMP
VCO
CHARGE
PUMP
VCO
LINK FAULT
DETECTION
DIVIDER
BY 8, 10, 16, 20
REFCLK
(TTL)
CD (PECL)
RDINN
RDINP
(PECL)
PLLR P/N
CLKSEL
(TTL)
RDOUTP
(PECL)
RCLKP
(PECL)
RCLKN
RDOUTN
PLLS P/N
DIVSEL 1/2
(TTL)
TCLKP
(PECL)
TCLKN
V
CC
V
CCA
V
CCO
GND
1
0
0
1
FPHASE/
DETECTOR
LFIN
(TTL)
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