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參數(shù)資料
| 型號： | SY604JC TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 255TAP 28-PLCC |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 標(biāo)片/步級數(shù)： | 255 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 4ns |
| 接頭增量： | 15.7ps |
| 可用的總延遲： | 4ns ~ 40ns |
| 獨立延遲數(shù)： | 1 |
| 電源電壓： | 4.2 V ~ 5.7 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY604JCTR SY604JCTR-ND |
Rev.: E
Amendment: /0
Issue Date: May, 1998
125MHz TRIGGER
PROGRAMMABLE TIMING
EDGE VERNIER
SY604
FINAL
DESCRIPTION
FEATURES
Micrel-Synergy's SY604 is an ECL-compatible timing vernier
(delay generator) whose time delay is programmed via an 8-
bit code which is loaded concurrently with the circuit trigger.
The SY604 is fabricated in Micrel-Synergy's proprietary
ASSET bipolar process.
This device can be retriggered at speeds up to 125MHz,
with a delay span as short as 4ns. At minimum span, the
resolution is 4ns/255 = 15.7ps per step. The delay span is
externally adjustable up to 40ns. The SY604 employs
differential TRIGGER inputs, and produces a differential
OUTPUT pulse; all other control signals are single-ended
ECL. Edge delay is specified by an 8-bit input which is loaded
into the device with the TRIGGER. The output pulse width will
typically be 3.5ns.
The SY604 is commonly used in Automatic Test Equipment
to provide precise timing edge placement; it is also found in
many instrumentation and communications applications.
Micrel-Synergy's circuit design techniques coupled with
ASSET technology result in not only ultra-fast performance,
but allow device operation at lower power dissipation than
competing technologies. Outstanding reliability is achieved in
volume production.
s True 125MHz retrigger rate
s Pin-compatible with Bt604
s 15ps delay resolution
s Less than
± 1 LSB timing accuracy
s Differential TRIGGER inputs
s Delay spans from 4 to 40ns
s Compatible with 10KH ECL logic
s Lower power dissipation 350mW typical
s Available in 28-pin plastic (PLCC) or metal (MLCC)
J-lead package
BLOCK DIAGRAM
PIN CONFIGURATION
LATCH
I/V
8
+
–
LINEAR
RAMP
GENERATOR
D
R
FF
0 = STOP
1 = RUN
OUT
IEXT
D0 - D7
CE
TRIG
VBB
PULSE
GEN
DAC
OUT
V
CC
V
CC
V
CC
NC
D0
TRIG
D
7
V
EE1
CE
COMP1
NC
VBB
NC
COMP2
IEXT
V
CC
D1
D2
D3
D4
D5
D6
18
17
16
15
14
13
12
56
7
8
9
10 11
26
27
28
1
2
3
4
TOP VIEW
PLCC
J28-1
25 24 23
21 20 19
22
V
EE1
TRIG
V
EE0
V
EE0
1
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參數(shù)描述 |
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| SY604JZ | 功能描述:延遲線/計時元素 125MHz Trigger Programmable Timing Edge Vernier (Lead Free) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
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| SY605JC | 功能描述:IC DELAY LINE 255TAP 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY605JC TR | 功能描述:IC DELAY LINE 255TAP 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
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