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參數(shù)資料
| 型號： | SY58621L |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | Precision 3.2Gbps CML/LVPECL Backplane Transceiver with Integrated Loopback |
| 中文描述： | 精密達(dá)3.2Gbps CML / LVPECL信號背板收發(fā)器集成環(huán)回 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 308K |
| 代理商： | SY58621L |
Micrel, Inc.
SY58621L
January 2006
12
M9999-012006-B
hbwhelp@micrel.com
or (408) 955-1690
LOS detection trip-point by setting up a voltage divider
between VCC and V
REF
(an internal voltage source set
at V
CC
-1.3V), since there is a 2.8k
internal resistor
connected between LOSLVL and V
REF
. The input
voltage range of LOSLVL ranges from V
CC
to V
REF
.
See the “Functional Block Diagram” section and
Figures 2a and 2b, to see how R
LOSLVL
sets up a
voltage divider between VCC and V
REF
. See the “LOS
Output DC Electrical Characteristics” table and
“Typical Operating Characteristics” section to see how
different R
LOSLVL
values affect LOS sensitivity.
Figure 2a. Voltage Source Implementation
Figure 2b. Alternative Implementation
LOS Output
Connecting the input /RXEN to the LOS output as
shown in Figures 2a and 2b, maintains receiver
output stability under a Loss-of-Signal condition
Sensitivity of the LOS signal can be programmed
using the LOSLVL input by using a variable resistor
connected to VCC with a wiper connected to
LOSLVL, as shown in Figure 2b
≥
2dB hysteresis is insured if R
LOSLVL
≤
10k
LOS is guaranteed chatter-free at f
≥
622Mbps
(311MHz)
Hysteresis
The SY58621L provides a minimum of 2dB of LOS
hysteresis, see the Figure 3 for more details.
Figure 3. LOS Hysteresis Assert/De-assert
Hysteresis is defined as: 20
Log
10
dB.
age
assertVolt
SD_De
oltage
SD_AssertV
Loopback
To support diagnostic system testing, the SY58621L
features a loopback test mode, activated by setting
LOOPBACK to logic HIGH. Loopback mode enables
an internal loopback path from the transmitter input to
the receiver output and supports the full 3.2Gbps data
rate throughput.
Crosstalk
The SY58621L features a patent-pending isolation
between the receiver and transmitter channels. The
following guide lines can be used to minimize on
layout induced crosstalk:
1. Ground Stripping
Ground stripping is an effective method to reduce
crosstalk. Ground stripping involves running a
ground trace between the receiver and transmitter
channels.
2. Vertical and Horizontal Traces
Another way to reduce crosstalk is to route the
receiver and transmitter channels on separate
layers with an embedded ground or power supply
layer between the layers. When routing the traces
on different layers, run the receiver traces
horizontal to the transmitter traces and route the
transmitter traces vertical to the receiver traces.
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| SY58621LMG | Precision 3.2Gbps CML/LVPECL Backplane Transceiver with Integrated Loopback |
| SY58621LMGTR | Precision 3.2Gbps CML/LVPECL Backplane Transceiver with Integrated Loopback |
| SY58626L | DC-to-6.4Gbps Backplane Transmit Buffer with Selectable Output Pre-emphasis, I/O DCOffset Control, and 200mV-3.0VPP Output Swing |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY58621L_10 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision 3.2Gbps CML/LVPECL Backplane |
| SY58621LMG | 功能描述:總線收發(fā)器 4.25Gbps Transceiver w/ CML/LVPECL Outputs (I Temp, Green) RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SY58621LMG TR | 功能描述:總線收發(fā)器 4.25Gbps Transceiver w/ CML/LVPECL Outputs (I Temp, Green) RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SY58621LMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision 3.2Gbps CML/LVPECL Backplane Transceiver with Integrated Loopback |
| SY58626L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:DC-to-6.4Gbps Backplane Transmit Buffer with |
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