hbwhelp@micrel.com or (408) 955-1690
參數(shù)資料
型號(hào): SY58611UMG
廠商: Micrel Inc
文件頁數(shù): 6/13頁
文件大?。?/td> 0K
描述: IC MUX 2:1 LVDS FSI INPUT 16-MLF
標(biāo)準(zhǔn)包裝: 100
系列: SY58
類型: 多路復(fù)用器
電路: 2 x 2:1
獨(dú)立電路: 1
電壓電源: 單電源
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤,16-MLF?
供應(yīng)商設(shè)備封裝: 16-MLF?(3x3)
包裝: 管件
產(chǎn)品目錄頁面: 1089 (CN2011-ZH PDF)
其它名稱: 576-2053-5
SY58611UMG-ND
Micrel, Inc.
SY58611U
March 2007
2
M9999-030607-A
hbwhelp@micrel.com or (408) 955-1690
Ordering Information(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead
Finish
SY58611UMG
QFN-16
Industrial
611U with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
SY58611UMGTR
(2)
QFN-16
Industrial
611U with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
16-Pin QFN
Truth Table
SEL
Output
0
IN0 Selected
1
IN1 Selected
Pin Description
Pin Number
Pin Name
Pin Function
1, 4
VT0, VT1
Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin.
This pin provides a center-tap to a termination network for maximum interface flexibility. See
“Input Interface Applications” subsection.
2, 3
VREF-AC0,
VREF-AC1
Reference Voltage: These outputs bias to VCC–1.2V. They are used for AC-coupling inputs IN
and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01F low ESR
capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to drive its
respective VT pin. Maximum sink/source current is ±0.5mA. See “Input Interface Applications”
subsection.
5, 6
15, 16
IN1, /IN1
IN0, /IN0
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
accept AC- or DC-Coupled differential signals as small as 100mV (200mVPP). Each pin of the
pairs internally terminates with 50 to the VT pin. If the input swing falls below a certain
threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by
latching the output to its last valid state. See “Input Interface Applications” subsection.
7
SEL
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default
to logic HIGH state if left open. The input-switching threshold is VCC/2.
8, 13
VCC
Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to the VCC pins
as possible.
9, 12
/Q, Q
LVDS Differential Output Pair: Differential buffered output copy of the selected input signal. The
output swing is typically 325mV. Normally terminated 100_ across the output (Q and /Q). See
“LVDS Output Interface Applications” subsection.
10, 11
GND,
Exposed pad
Ground. Exposed pad must be connected to a ground plane that is the same potential as the
ground pin.
14
NC
No connect.
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