CML Electrical Characteristics (5)
參數(shù)資料
型號: SY58051UMG
廠商: Micrel Inc
文件頁數(shù): 7/10頁
文件大?。?/td> 0K
描述: IC GATE CML UNIV I/O TERM 16MLF
標(biāo)準(zhǔn)包裝: 100
系列: SY58
邏輯類型: 可配置多功能
電路數(shù): 1
輸入數(shù): 2
施密特觸發(fā)器輸入:
輸出類型: 差分
電源電壓: 2.3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤,16-MLF?
供應(yīng)商設(shè)備封裝: 16-MLF?(3x3)
包裝: 托盤
產(chǎn)品目錄頁面: 1089 (CN2011-ZH PDF)
其它名稱: 576-1398
Micrel, Inc.
SY58051U-A
July 2011
6
M9999-071311U-A
hbwhelp@micrel.com
CML Electrical Characteristics (5)
VCC = 2.5V ±5% or 3.3V ±10%; RL =100 across output pair or equivalent; TA = -40°C to +85°C; unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ
Max
Units
VCH
Output HIGH Voltage Q, /Q
VCC—0.020
VCC 3.6
V
VOUT
Output Voltage Swing Q, /Q
See Figure 2a.
325
400
500
mV
VDIFF_OUT
Differential Output Voltage Swing
Q, /Q
See Figure 2b.
650
800
1000
mV
ROUT
Output Source Impedance
Q, /Q
40
50
60
AC Electrical Characteristics (8)
VCC = 2.5V ±5% or 3.3V ±10%; RL =100 across output pair or equivalent; TA = -40°C to +85°C; unless otherwise noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
FMAX
Maximum Operating Frequency
Clock
NRZ Data
10.7
7
GHz
Gbps
tpd
Propagation Delay Any Input
(A, B, S)-to-Q
70
190
ps
tSKEW
Part-to-Part Skew
Note 9
100
ps
Data
Random Jitter (RJ)
Note 10
1
psRMS
Deterministic Jitter (DJ)
Note 11
10
psPP
Clock
Cycle-to-Cycle Jitter (RJ)
Note 12
1
psRMS
tJITTER
Total Jitter (TJ)
Note 13
10
psPP
TR, tf
Output Rise/Fall Times (20% to 80%)
At full output swing.
20
60
ps
Notes:
7.
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
8.
Measured with 100mV input swing. See “Timing Diagrams” section for definition of parameters. High-frequency AC parameters are guaranteed by
design and characterization.
9.
Skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
10. Random jitter is measured with a K28.7 comma detect character pattern, measured at 2.5Gbps/3.2Gbps.
11. Deterministic jitter is measured at 2.5Gbps/3.2Gbps with both K28.5 and 2
23–1 PRBS pattern.
12. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn–Tn–1 where T is the time between rising edges of the output
signal.
13. Total jitter definition: with an ideal clock input of frequency
fMAX, no more than one output edge in 10
12 output edges will deviate by more than the
specified peak-to-peak jitter value.
or (408) 955-1690
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