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參數(shù)資料
型號(hào): SY58034UMG
廠商: Micrel Inc
文件頁(yè)數(shù): 4/11頁(yè)
文件大小: 0K
描述: IC CLK BUFF MUX 2:6 7.5GHZ 32MLF
標(biāo)準(zhǔn)包裝: 60
系列: Precision Edge®
類(lèi)型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 2:6
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,PECL
輸出: CML
頻率 - 最大: 7.5GHz
電源電壓: 2.375 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán),32-MLF?
供應(yīng)商設(shè)備封裝: 32-MLF?(5x5)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1083 (CN2011-ZH PDF)
其它名稱(chēng): 576-1391
2
Precision Edge
SY58034U
Micrel, Inc.
M9999-082707
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package Operating
Package
Lead
Part Number
Type
Range
Marking
Finish
SY58034UMG
QFN-32
Industrial
SY58034U with
NiPdAu
Pb-free bar-line indicator Pb-Free
SY58034UMGTR(2)
QFN-32
Industrial
SY58034U with
NiPdAu
Pb-free bar-line indicator Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only.
2. Tape and Reel.
Pin Number
Pin Name
Pin Function
1, 4
IN0, /IN0
Differential Input: These input pairs are the differential signal inputs to the device. These
5, 8
IN1, /IN1
inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally
terminates to a VT pin through 50. Note that these inputs will default to an indeterminate
state if left open. Please refer to the “Input Interface Applications” section for more details.
2, 6
VT0, VT1
Input Termination Center-Tap: Each side of the differential input pair terminates to a VT
pin. The VT0 and VT1 pins provide a center-tap to a termination network for maximum
interface flexibility. See “Input Interface Applications” section for more details.
31
SEL
This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note
that this input is internally connected to a 25k pull-up resistor and will default to a logic
HIGH state if left open. The MUX select switchover function is asynchronous.
10
NC
No connect.
11, 16, 18,
VCC
Positive Power Supply: Bypass with 0.1F 0.01F low ESR capacitors and place as
.
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b
i
s
o
p
s
a
s
n
i
p
C
V
e
h
t
o
t
e
s
o
l
c
0
3
,
5
2
,
3
2
29, 28
Q0, /Q0,
Differential Outputs: These CML output pairs are low skew output copies of the selected
27, 26
Q1, /Q1,
input. The output stage is optimized to deliver a 400mV swing (single-ended) into 50.
22, 21
Q2, /Q2,
Each output includes a 50 source-termination resistor, thus minimizing any return
20, 19
Q3, /Q3,
reflections. Unused output pins may be left floating. Please refer to the “Truth Table”
15, 14
Q4, /Q4,
for details.
13, 12
Q5, /Q5
9, 17, 24, 32
GND,
Ground. Ground pin and exposed pad must be connected to the same ground plane.
Exposed Pad
3, 7
VREF-AC0,
Reference Voltage: These output biases to VCC–1.2V. It is used for AC-coupling inputs
VREF-AC1
(IN, /IN). Connect VREF-AC directly to the VT pin. Bypass with 0.01F low ESR capacitor to
VCC. See “Input Interface Applications” section. Maximum sink/source current is ±1.5mA.
Due to the limited capability, the VREF-AC pin is only intended to drive its respective VT
pin.
PIN DESCRIPTION
24
23
22
21
20
19
18
17
GND
VCC
Q2
/Q2
Q3
/Q3
VCC
GND
IN0
VT0
VREF-AC0
/IN0
IN1
VT1
VREF-AC1
/IN1
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
/Q0
Q0
VCC
SEL
GND
Q1 /Q1 VCC
Q5
/Q5
VCC
NC
GND
/Q4 Q4
VCC
32-Pin QFN
TRUTH TABLE
SEL
0
IN0 Input Selected
1
IN1 Input Selected
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