Precision Edge SY58027U Micrel, Inc. M9999-082707 hbwhelp@micrel.com or (408) 955-1690 TRUTH TABLES I" />
參數(shù)資料
型號: SY58027UMG
廠商: Micrel Inc
文件頁數(shù): 6/10頁
文件大?。?/td> 0K
描述: IC MUX DUAL 2:1 DFF LVPECL 32MLF
標準包裝: 60
系列: SY58
類型: 多路復(fù)用器
電路: 1 x 2:1
獨立電路: 2
電壓電源: 單電源
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,32-MLF?
供應(yīng)商設(shè)備封裝: 32-MLF?(5x5)
包裝: 管件
產(chǎn)品目錄頁面: 1089 (CN2011-ZH PDF)
其它名稱: 576-1384
5
Precision Edge
SY58027U
Micrel, Inc.
M9999-082707
hbwhelp@micrel.com or (408) 955-1690
TRUTH TABLES
INA0
/INA0
INA1
/INA1
SELA
QA
/QA
01
X
0
1
10
X
0
1
0
XX
0
1
0
1
XX
1
0
1
0
INB0
/INB0
INB1
/INB1
SELB
QB
/QB
01
X
0
1
10
X
0
1
0
XX
0
1
0
1
XX
1
0
1
0
AC ELECTRICAL CHARACTERISTICS(7)
VCC = 2.5V ±5% or 3.3V ±10%; TA= –40°C to +85°C; RL = 50 to VCC–2V, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Operating Frequency
NRZ Data
10.7
Gbps
VOUT 200mV
Clock
7
GHz
tpd
Propagation Delay
IN-to-Q
VIN 300mV
140
215
290
ps
SEL-to-Q
100
220
400
ps
tSKEW
Input-to-Input Skew (Within-bank)
Note 8
615
ps
Bank-to-Bank Skew
Note 9
820
ps
Part-to-Part Skew
Note 10
100
ps
tJITTER
Data
Random Jitter (RJ)
Note 11
1psRMS
Deterministic Jitter (DJ)
Note 12
10
psPP
Clock
Cycle-to-Cycle Jitter (RJ)
Note 13
1psRMS
Total Jitter (TJ)
Note 14
10
psPP
Crosstalk-Induced Jitter
Channel-to-Channel
Note 15, Within-bank.
0.7
psRMS
tr, tf
Output Rise/Fall Time 20% to 80%
At full swing.
20
55
80
ps
Notes:
7. High-speed AC parameters are guaranteed by design and characterization. VIN swing 100mV unless otherwise noted.
8. Input-to-input skew is the difference in time between two inputs to the output within a bank.
9. Bank-to-bank skew is the difference in time from input to the output between bank.
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
11. Random jitter is measured with a K28.7 comma detect character pattern, measured at 5Gbps and 2.5Gbps/3.2Gbps.
12. Deterministic jitter is measured at 2.5Gbps/3.2Gbps, with both K28.5 and 223–1 PRBS pattern.
13. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn–Tn–1 where T is the time between rising edges of the output
signal.
14. Total jitter definition: with an ideal clock input of frequency - fMAX, no more than one output edge in 10
12 output edges will deviate by more than the
specified peak-to-peak jitter value.
15. Crosstalk is measured at the output while applying two similar frequencies that are asynchronous with respect to each other at the inputs.
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