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參數(shù)資料
| 型號： | SY56034ARMG TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MULTIPLEXER 32MLF |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | Precision Edge® |
| 功能： | 多路復(fù)用器 |
| 電路： | 2 x 2:1 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 2.375 V ~ 2.625 V，1.14 V ~ 1.9 V |
| 電流 - 電源： | 100mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，32-MLF? |
| 供應(yīng)商設(shè)備封裝： | 32-MLF?（5x5） |
| 包裝： | 帶卷 (TR) |
Micrel, Inc.
SY56034AR
September 2008
6
M9999-093008-A
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
VCCO = 1.14V to 1.26V, RL = 50
to V
CCO,
VCCO = 1.7V to 1.9V, 2.375V to 2.625V, RL = 50
to V
CCO or 100
across the outputs.
VCC = 2.375V to 2.625V. TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Frequency
NRZ Data
6.4
Gbps
VOUT > 200mV
Clock
5
GHz
tPD
Propagation Delay
IN-to-Q
SEL-to-Q
Figure 1
150
220
300
ps
Figure 1
100
200
300
ps
tSkew
Input-to-Input Skew
Note 6
5
15
ps
Output-to-Output skew
Note 7, All Outputs or Q0-Q3
7
25
ps
Output-to-Output skew
Note 7, Q4-Q5
4
20
ps
Part-to-Part Skew
Note 8
75
ps
tJitter
Data
Random Jitter
Note 9
1
psRMS
Deterministic Jitter
Note 10
10
psPP
Clock
Cycle-to-Cycle Jitter
Note 11
1
psRMS
Total Jitter
Note 12
10
psPP
Crosstalk Induced Jitter
(Adjacent Channel)
Note 13
0.7
psPP
tR, tF
Output Rise/Fall Times
(20% to 80%)
At full output swing.
20
60
80
ps
Duty Cycle
≤4GHz Differential I/O
47
53
%
<5GHz Differential I/O
45
55
%
Notes:
6.
Input-to-Input skew is the difference in time between both inputs, measured at the same output, for the same temperature, voltage and
transition.
7.
Output-to-Output skew is the difference in time between both outputs, receiving data from the same input, for the same temperature, voltage and
transition.
8.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
9.
Random jitter is measured with a K28.7 pattern, measured at
≤ f
MAX.
10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23–1 PRBS pattern.
11. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,
where T is the time between rising edges of the output signal.
12. Total jitter definition: with an ideal clock input frequency of
≤ f
MAX (device), no more than one output edge in 10
12 output edges will deviate by
more than the specified peak-to-peak jitter value.
13. Crosstalk-induced jitter is defined as the added jitter that results from signals applied to the adjacent channel. It is measured at the output while
applying a similar, differential clock frequency to both inputs that is asynchronous with respect to each other.
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