參數(shù)資料
型號: SY54020RMGTR
廠商: MICREL INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: LOW SKEW CLOCK DRIVER, QCC16
封裝: 3 X 3 MM, LEAD FREE, MLF-16
文件頁數(shù): 8/14頁
文件大?。?/td> 550K
代理商: SY54020RMGTR
Micrel, Inc.
SY54020R
April 2009
3
M9999-041409-A
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
2,3
IN, /IN
Differential Input: This input pair is the differential signal input to the device. It
accepts differential signals as small as 100mV (200mVPP). Each input pin internally
terminates with 50
to the VT pin. If the input swing falls below a certain threshold
(typical 30mV), the Fail-Safe Input (FSI) feature will guarantee a stable output by
latching the output to its last valid state. Please refer to the “Interface Applications”
section for more details.
1
VT
Input Termination Center-Tap: Each side of the differential input pair terminates to
VT pin. This pin provides a center-tap to a termination network for maximum
interface flexibility. An internal high impedance resistor divider biases VT to allow
input AC coupling. For AC coupling, bypass VT with 0.1F low ESR capacitor to
VCC. See “Interface Applications” subsection and Figure 2a.
4
/EN
Single-ended TTL/CMOS-compatible input functions as a synchronous output
enable. The synchronous enable ensures that enable/disable will only occur when
the outputs are in a logic LOW state. The input -switching threshold is Vcc/2. Note
that this input is internally connected to a 25k
pull-down resistor and will default to
a logic LOW state (Enabled) if left open. Outputs are disabled when /EN is high.
See Figure 1b for more details.
16
VCC
Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to
the VCC pin as possible. Supplies input and core circuitry.
8,13
VCCO
Output Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to the VCCO
pin as possible. Supplies the output buffers.
5
GND,
Exposed pad
Ground: Exposed pad must be connected to a ground plane that is the same
potential as the ground pin.
15,14
12,11
10,9
7,6
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
CML Differential Output Pairs: Differential buffered copy of the input signal. The
output swing is typically 380mV. See “Interface Applications” subsection for
termination information.
Truth Table
IN
/IN
/EN
Q
/Q
0
1
0
1
0
1
0
X
1
0
(1)
1
(1)
Note:
1. See timing diagram, Figure 1b.
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