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參數(shù)資料
| 型號(hào)： | SY15-S3 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁(yè)數(shù)： | 2/6頁(yè) |
| 文件大?。?/td> | 169K |
| 代理商： | SY15-S3 |
SYNCHRONOUS EQUIPMENT
STRATUM 3 CLOCK UNIT WITH HF OUTPUTS – SY15-S3
RALTRON ELECTRONICS CORP.
!
10651 N.W.19
th
St
!
Florida 33172
!
U.S.A.
Tel: 305 593-6033
!
Fax: 305-594-3973
!
e-mail: sales@raltron.com
!
Internet: http://www.raltron.com
Figure 1. - The functional block diagram of SY15-S3
The SY15-S3 synchronization module is a Digital PLL (DPLL), which utilizes application specific software in the
digital signal processor (DSP). The DSP is complemented by fast hardware logic (CPLD) where all multiplexers,
counters, dividers, phase detectors, and other control logic circuits are completely implemented. The functional
block diagram with configuration is shown in figure 1. The configuration utilizes one DPLL with an OCXO as on-
board oscillator, and one high frequency synthesizer. The OCXO is driven by a digital-to-analog converter (DAC1)
and provides the accurate and stable signal under all conditions. The output frequencies are generated by the
synthesizer that uses a VCXO and high frequency dividers to provide the output frequencies on all three outputs.
For other configurations, please contact Raltron.
"
The module operates in the following four timing modes:
Free-run
In this mode the unit is unlocked to either of the inputs. The accuracy of the output frequencies in this mode is
±4.6ppm. Free-run mode is typically used when a master clock source is required, not valid history of data for the
Holdover mode, or immediately following system power-up before network synchronization is achieved. In the Free-
run Mode, the SY15-S3 provides timing and synchronization signals that are based on the accuracy of on-board
oscillators only, and are not synchronized to the reference signals.
Holdover
In this mode the module has lost its reference inputs and is utilizing stored timing data, called history, to control the
output frequency. Holdover Mode is typically used while network synchronization is temporarily disrupted. In
Holdover Mode, the SY15-S3 provides timing, based on data from the history buffer, while unlocked to an external
reference signal. The history data is determined while the device is locked to an external reference signal. The
stability of the output signal in holdover mode depends primarily on the stability of on-board oscillator and
environment effects where the clock is mounted. The SY15-S3 uses an OCXO as an on-board oscillator but other
types of oscillators are available.
DESCRIPTION
÷
N
PD1
MUX
CONTROL
LOGIC
DSP
FLASH
RAM
DAC
1
OCXO
HIGH
FREQUENCY
SYNTHESIZER
EX REF1
EX REF2
EX REF3
CNT1
CNT2
ALARM OUT
PLL UNLOCK
REF 1 to
REF 5
J-TAG
OUT 1
DIV
OUT 2
OUT 3
CPLD
ENOUT1
ENOUT2
ENOUT3
CNT3
EX REF4
EX REF5
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