參數(shù)資料
型號: SY10EL15ZITR
廠商: MICREL INC
元件分類: 時鐘及定時
英文描述: 1:4 CLOCK DISTRIBUTION
中文描述: 10EL SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝: 0.150 INCH, SOIC-16
文件頁數(shù): 1/4頁
文件大?。?/td> 63K
代理商: SY10EL15ZITR
The SY10/100EL15 are low skew 1:4 clock distribution
chips designed explicitly for low skew clock distribution
applications. The device can be driven by either a
differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. If a single-ended
input is to be used the V
BB
output should be connected
to the CLK input and bypassed to V
CC
via a 0.01
μ
F
capacitor. The V
BB
output is designed to act as the
switching reference for the input of the EL15 under single-
ended input conditions, as a result this pin can only
source/sink up to 0.5mA of current.
The EL15 features a multiplexed clock input to allow
for the distribution of a lower speed scan or test clock
along with the high speed system clock. When LOW (or
left open and pulled LOW by the input pull-down resistor)
the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the
outputs will only be enabled/disabled when they are
already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.
The internal flip flop is clocked on the falling edge of the
input clock, therefore all associated specification limits
are referenced to the negative edge of the clock input.
Pin
Function
CLK
Differential Clock Inputs
SCLK
Synchronous Clock Input
EN
Synchronous Enable
SEL
Clock Select Input
V
BB
Reference Output
Q
0-3
Differential Clock Outputs
TRUTH TABLE
PIN NAMES
FEATURES
DESCRIPTION
PIN CONFIGURATION/BLOCK DIAGRAM
Precision Edge
SY10EL15
SY100EL15
FINAL
CLK
SCLK
SEL
EN
Q
L
X
L
L
L
H
X
L
L
H
X
L
H
L
L
X
H
H
L
H
X
X
X
H
L*
* On next negative transition of CLK or SCLK
V
CC
16
CLK
13
Q
0
Q
0
Q
1
Q
2
Q
2
Q
3
Q
3
V
EE
9
SEL
10
V
BB
11
CLK
12
EN
15
14
Q
1
1
2
3
4
5
6
7
8
D
Q
1 0
SCLK
SOIC
TOP VIEW
I
50ps output-to-output skew
I
Synchronous enable/disable
I
Multiplexed clock input
I
75K
internal input pull-down resistors
I
Available in 16-pin SOIC package
1:4 CLOCK
DISTRIBUTION
1
Rev.: G
Issue Date:
Amendment: /0
February 2003
Precision Edge is a trademark of Micrel, Inc.
Precision Edge
相關PDF資料
PDF描述
SY10EL15 1:4 CLOCK DISTRIBUTION
SY10EL15ZC 1:4 CLOCK DISTRIBUTION
SY10EL16VAZCTR ER 37C 37#16 PIN PLUG RoHS Compliant: No
SY100EL16VAZCTR ER 37C 37#16 PIN PLUG
SY100EL16VSZC OSC 3.3V 8PIN PROG HCMOS
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