參數(shù)資料
型號(hào): SY100EP57VK4C
廠商: MICREL INC
元件分類: 通用總線功能
英文描述: 3.3V/5V PECL/ECL 3GHz DIFFERENTIAL 4:1 MULTIPLEXER
中文描述: 100E SERIES, 4 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20
封裝: TSSOP-20
文件頁數(shù): 2/8頁
文件大?。?/td> 214K
代理商: SY100EP57VK4C
2
ECL Pro
SY100EP57V
Micrel
PIN DESCRIPTION
Pin
Pin Number
Function
D0: D3
/D0: /D3
2, 4, 6, 8
3, 5, 7, 9
Input Channels 0-3 PECL/ECL differential signal inputs. Multiplexing of these 4 differential inputs
is controlled by SEL0, SEL1. The signal inputs include internal 75k
pull-down resistors. Default
condition is LOW when left floating. The input signal should be terminated externally.
See
Termination
section
VEE
10, 11
Negative Power Supply: For PECL/LVPECL applications, connect to Ground. Both V
EE
pins must
be connected together, externally on the PCB, for proper operation.
VBB1, VBB2
13, 12
Reference output voltage. This reference is typically used to bias the unused inverting input for
single-ended input applications, or as the termination point for AC
coupled differential input
applications. V
BB
reference value is approximately V
CC
1.4V, and tracks V
CC
1:1. Maximum sink/
source capability for each V
BB
reference pin is 0.50mA. For single ended PECL inputs, connect to
the unused input through a 50
resistor. Decouple the V
BB
pin with a 0.01
μ
F capacitor. For PECL/
LVPECL inputs, the decoupling capacitor is connected to V
CC
, since PECL signals are referenced
to V
CC
. Leave floating if not used.
100KEP PECL/ECL compatible differential output. PECL/ECL termination is with a 50
resistor to V
CC
2V. Unused single-ended outputs must have a balanced load. For AC
coupled
applications, the output stage emitter follower must have a DC current path to ground.
See
Termination
section.
/Q, Q
15, 16
SEL0, SEL1
18, 19
100KEP PECL/ECL compatible 4:1 MUX select control. See
MUX Select Truth Table.
Each pin
includes an internal 75k
pull-down resistor. Default condition when left floating is LOW.
VCC
1, 14, 17, 20
Positive Power Supply. All V
CC
pins must be connected to the same power supply externally.
Bypass with 0.1
μ
F//0.01
μ
F low ESR capacitors.
MUX SELECT TRUTH TABLE
SEL1
SEL0
DATA OUT
L
L
D0, /D0
L
H
D1, /D1
H
L
D2, /D2
H
H
D3, /D3
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