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參數(shù)資料
| 型號(hào)： | SY100EP196VTCTR |
| 廠商： | MICREL INC |
| 元件分類： | 延遲線 |
| 英文描述： | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 179K |
| 代理商： | SY100EP196VTCTR |
3
ECL Pro
SY100EP196V
Micrel
Pin Number
Pin Name
Pin Function
23, 25, 26, 27, 29,
D[0:9]
CMOS, ECL, or TTL Select Inputs: These digital control signals adjust the amount of
30, 31, 32, 1, 2
delay from IN to Q. Please refer to the delay selection Table 1 for delay values. Figure 9
shows how to interface these inputs to various logic family standards. These inputs default
to logic low when left unconnected. Bit 0 is the least significant bit, and bit 9 is the most
significant bit.
3
D[10]
CMOS, ECL, or TTL Select Input: This input latches just like D[0:9] does. It drives the
CASCADE, /CASCADE differential pair. Use only when cascading two or more
SY100EP196V to extend the range of delays required.
4, 5
IN, /IN
ECL Input: This is the signal to be delayed. If this input pair is left unconnected, this is
equivalent to a logic low input.
6
VBB
Voltage Output Reference: When using a single-ended logic source for IN and /IN,
connect the unused input of the differential pair to this pin. This pin can also re-bias AC–
coupled inputs to IN and /IN. When used, de-couple this pin to V
CC through an 0.01F
capacitor. Limit current sinking or sourcing to 0.5mA or less.
7
VEF
Voltage Output: Connect this pin to VCF when the D inputs are ECL. Refer to the digital
control logic standard section of the Functional Description to interface the D inputs to
CMOS or TTL.
8
VCF
Voltage Input: The voltage at this pin sets the logic transition threshold for the D inputs.
9, 24, 28
VEE
Most negative supply. Supply ground for PECL systems.
10
LEN
ECL Control Input: When logic low, the D inputs flow through. Any changes to the D inputs
reflect in the delay between IN, /IN and Q, /Q. When logic high, the logic values at D are
latched, and these latched bits determine the delay.
11
SETMIN
ECL Control Input: When logic high, the contents of the D register are reset. This sets the
delay to the minimum possible, equivalent to D[0:9] being set to 0000000000. When logic
low, the value of the D register, or the logic value of SETMAX determines the delay from
IN, /IN to Q, /Q. This input defaults to logic low when left unconnected.
12
SETMAX
ECL Control Input: When logic high and SETMIN is logic low, the contents of the D
register are set high, and the delay is set to one step greater than the maximum possible
with D[0:9] set to 1111111111. When logic low, the value of the D register, or the logic
value of SETMIN determines the delay from IN, /IN to Q, /Q. This input defaults to logic
low when left unconnected.
13, 18, 19, 22
VCC
Most positive supply: Supply ground for NECL systems. Bypass to V
EE with 0.1F and
0.01
F low ESR capacitors.
14, 15
CASCADE,
ECL Outputs: These outputs are used when cascading two or more SY100EP196V to
/CASCADE
extend the delay range required.
16
/EN
ECL Control Input: When set active low, Q, /Q are a delayed version of IN, /IN. When set
inactive high, IN, /IN are gated such that Q, /Q become a differential logic low. This input
defaults to logic low when left unconnected.
17
FTUNE
Voltage Control Input: By varying the voltage at this pin from V
CC through VEE, the delay
may be fine tuned in about a 30ps range. Please refer to Figure 13.
20, 21
Q, /Q
ECL Outputs: This signal pair is the delayed version of IN, /IN.
PIN DESCRIPTION
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