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參數(shù)資料
| 型號： | SY100EP195VTG |
| 廠商： | MICREL INC |
| 元件分類： | 延遲線 |
| 英文描述： | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 701K |
| 代理商： | SY100EP195VTG |
15
ECL Pro
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
For best performance, use good high frequency layout
techniques, filter VCC supplies, and keep ground connections
short. Use multiple vias where possible. Also, use controlled
impedance transmission lines to interface with the
SY100EP195V data inputs and outputs.
VBB Supply
The VBB pin is an internally generated supply, and is
available for use only by the SY100EP195V. When unused,
this pin should be left unconnected. The two common uses
for VBB are to handle a single-ended PECL input, and to re-
bias inputs for AC-coupling applications.
If IN, /IN is driven by a single-ended output, VBB is used
to bias the unused input. Please refer to Figures 7. The
PECL signal driving SY100EP195V may optionally be
inverted in this case.
When the signal is AC-coupled, VBB is used, as shown
in Figure 8, to re-bias IN, /IN. This ensures that
SY100EP195V inputs are within its acceptable common
mode range.
In all cases, VBB current sinking our sourcing must be
limited to 0.5mA or less.
APPLICATIONS INFORMATION
IN
/IN
Q
/Q
IN
/IN
Q
/Q
D[9:0]
SY100EP195V
#2
#1
SETMIN
SETMAX
/CASCADE
CASCADE
D[10]
C[9:0]
C[10]
Control Word (11bits)
Figure 10a. Cascading Two SY100EP195V
IN
/IN
Q
/Q
IN
/IN
Q
/Q
SY100EP195V
#3
#2
SETMIN
SETMAX
SETMIN
SETMAX
/CASCADE
CASCADE
D[10]
C[11]
IN
/IN
Q
/Q
D[9:0]
SY100EP195V
#1
/CASCADE
CASCADE
D[10]
C[9:0]
C[10]
Control Word (12bits)
Figure 10b. Cascading Three SY100EP195V
Setting D Input Logic Thresholds
As explained earlier, in all designs where the
SY100EP195V VEE supply is at zero volts, the D inputs
may accommodate CMOS and TTL level signals, as well as
PECL or LVPECL. Figures 9 show how to connect VCF and
VEF for all possible cases.
Cascading
Two or more SY100EP195V may be cascaded, in order
to extend the range of delays permitted. Each additional
SY100EP195V adds about 2200ps to the minimum delay,
and adds another 10240ps to the delay range.
Internal cascade circuitry has been included in the
SY100EP195V. Using this internal circuitry, SY100EP195V
may be cascaded without any external gating.
Examples of cascading 2, 3, or 4 SY100EP195V appear
in Figures 10. Table 7 lists the nominal delay for all the
cases that appear in Figures 10.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SY100EP195VTG TR | 功能描述:延遲線/計時元素 3.3V/5V 2.5 GHz Programmable Delay Line (I Temp, Green) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY100EP195VTI | 功能描述:IC DELAY LINE 1024TAP 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:100EP, ECL Pro® 標準包裝:2,500 系列:- 標片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY100EP195VTI TR | 功能描述:IC DELAY LINE 1024TAP 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:100EP, ECL Pro® 標準包裝:2,500 系列:- 標片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY100EP196VTG | 功能描述:延遲線/計時元素 3.3V/5V 2.5 GHz Programmable Delay Line w/Fine Tune (I Temp, Green) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY100EP196VTG TR | 功能描述:延遲線/計時元素 3.3V/5V 2.5 GHz Programmable Delay Line w/Fine Tune (I Temp, Green) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
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