參數(shù)資料
型號(hào): SY100EL91LZG
廠商: Micrel Inc
文件頁數(shù): 1/6頁
文件大?。?/td> 0K
描述: IC TRANSLATOR TRIPLE 20-SOIC
標(biāo)準(zhǔn)包裝: 38
系列: 100EL
邏輯功能: 變換器
位數(shù): 3
輸入類型: LVPECL
輸出類型: ECL,LVECL
通道數(shù): 3
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 是/是
傳輸延遲(最大): 0.62ns
電源電壓: 3 V ~ 3.8 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC(寬型)
包裝: 管件
產(chǎn)品目錄頁面: 1088 (CN2011-ZH PDF)
其它名稱: 576-2456
SY100EL91LZG-ND
1
SY100EL91L
Micrel, Inc.
M9999-031306
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
s 3.3V power supply
s 620ps propagation delay
s Fully differential design
s Supports low voltage operation
s Available in 20-pin SOIC package
The SY100EL91L is a triple LVPECL-to-ECL or
LVPECL-to-LVECL translator.
A VBB output is provided for interfacing with single
ended PECL signals at the input. If a single ended input
is to be used, the VBB output should be connected to the
D input. The active signal would then drive the D input.
When used, the VBB output should be bypassed to ground
via a 0.01
F capacitor. The VBB output is designed to act
as the switching reference for the EL91L under single
ended input switching conditions. As a result this pin can
only source/sink up to 0.5mA of current.
To accomplish the level translation the EL91L requires
three power rails. The VCC supply should be connected
to the positive supply, and the VEE pin should be
connected to the negative power supply. The GND pins
as expected are connected to the system ground plane.
Both VEE and VCC should be bypassed to ground via
0.01
F capacitors.
Under open input conditions, the D input will be biased
at VCC/2 and the D input will be pulled to GND. This
condition will force the Q output to a LOW, ensuring
stability.
FEATURES
3.3V TRIPLE LVPECL-to-ECL
OR LVPECL-to-LVECL TRANSLATOR
Pin
Function
Dn
PECL Inputs
Qn
ECL Outputs
PECL_VBB
PECL Reference Voltage Output
SY100EL91L
PIN NAMES
Function
Vcc
VEE
LVPECL-to-ECL
3.3V
–5.0V
LVPECL-to-LVECL
3.3V
–3.3V
FUNCTION TABLE
1
Rev.: H
Amendment: /0
Issue Date:
December 2005
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