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參數(shù)資料
| 型號(hào)： | SY100E196JC |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 10/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 7TAP 28-PLCC |
| 標(biāo)準(zhǔn)包裝： | 38 |
| 系列： | 100E, Precision Edge® |
| 標(biāo)片/步級(jí)數(shù)： | 7 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 1.39ns |
| 接頭增量： | 20ps |
| 可用的總延遲： | 1.39ns ~ 3.63ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | -4.2 V ~ -5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC |
| 包裝： | 管件 |
9
Precision Edge
SY10E196
SY100E196
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
delays (1111111 on the A0–A6 address bus), D7 will be
asserted to signal the need to cascade the delay to the
next E196 device. When D7 is asserted, the SET MIN
pin of chip #2 will be de-asserted and the delay will be
controlled by the A0–A6 address bus. Chip #1, on the
other hand, will have its SET MAX pin asserted, resulting
in the device delay to be independent of the A0–A6
address bus.
When the SET MAX pin of chip #1 is asserted, the D0
and D1 latches will be reset, while the rest of the latches
will be set.
In addition, to maintain monotonicity, an
additional gate delay is selected in the cascade circuitry.
As a result, when D7 of chip #1 is asserted, the delay
increases from 31.75 gates to 32 gates. A 32-gate delay
is the maximum delay setting for the E196.
When cascading multiple PDCs, it will prove more cost-
effective to use a single E196 for the MSB of the chain,
while using E195 for the lower order bits. This is due to
the fact that only one fine tune input is needed to further
reduce the delay step resolution.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY100E196JCTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT |
| SY100E196JI | 功能描述:IC DELAY LINE 7TAP 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 延遲線 系列:100E, Precision Edge® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級(jí)數(shù):- 功能:多個(gè)，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY100E196JITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT |
| SY100E196JY | 功能描述:延遲線/計(jì)時(shí)元素 Programmable Delay Chip (I Temp, Lead Free) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY100E196JYTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT |
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