參數(shù)資料
型號: SY100E175JZ
廠商: MICREL INC
元件分類: 通用總線功能
英文描述: 9-BIT LATCH WITH PARITY
中文描述: 100E SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PQCC28
封裝: LEAD FREE, PLASTIC, LCC-28
文件頁數(shù): 1/4頁
文件大小: 70K
代理商: SY100E175JZ
1
SY10E175
SY10E175
SY100E175
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Pin
Function
D
0
– D
8
Data Inputs
LEN
Latch Enable
MR
Master Reset
Q
0
– Q
8
Data Outputs
ODDPAR
Parity Output
V
CCO
V
CC
to Output
DESCRIPTION
FEATURES
I
9-bit latch
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
Parity detection/generation
I
800ps max. D to Output
I
Reset
I
Internal 75K
input pull-down resistors
I
Fully compatible with Motorola MC10E/100E175
I
Available in 28-pin PLCC package
The SY10/100E175 are 9-bit latches. They also feature
a tenth latched output (ODDPAR) which is formed as the
odd parity of the nine data inputs (ODDPAR is HIGH if
an odd number of the inputs are HIGH).
The E175 can also be used to generate byte parity by
using D
8
as the parity-type select (L = even parity, H =
odd parity) and using ODDPAR as the byte parity output.
The LEN pin latches the data when asserted with a
logical high and makes the latch transparent when placed
at a logic low level.
9-BIT LATCH
WITH PARITY
BLOCK DIAGRAM
ODDPAR
D
0
LEN
MR
Q
8
Q
0
D
8
bits
1
7
D
EN
Q
R
D
EN
Q
R
D
EN
Q
R
PIN NAMES
Rev.: F
Issue Date:
Amendment: /0
March 2006
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