參數(shù)資料
型號: SY100E112JI TR
廠商: Micrel Inc
文件頁數(shù): 1/4頁
文件大?。?/td> 0K
描述: IC BUFF/DVR 4BIT N-INVERT 28PLCC
標(biāo)準包裝: 750
系列: 100E
邏輯類型: 緩沖器/線路驅(qū)動器,非反相
元件數(shù): 1
每個元件的位元數(shù): 4
電源電壓: 4.2 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC
包裝: 帶卷 (TR)
其它名稱: SY100E112JITR
SY100E112JITR-ND
1
SY10E112
SY100E112
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
FEATURES
s 600ps max. propagation delay
s Extended 100E VEE range of –4.2V to –5.5V
s Common enable input
s Fully compatible with industry standard 10KH, 100K
I/O levels
s Internal 75K
input pulldown resistors
s Fully compatible with Motorola MC10E/100E112
s Available in 28-pin PLCC package
The SY10/100E112 are quad drivers designed for use
in new, high-performance ECL systems. The E112 has two
pairs of OR/NOR outputs from each gate and a common,
buffered enable input. The data input can also be used as
an ECL memory address fan-out driver, although the E111
is designed specifically for this purpose, and offers lower
skew than the E112. For memory address driver applications
where scan capabilities are required, please refer to the
SY10/100E212 device.
QUAD
DRIVER
SY10E112
SY100E112
DESCRIPTION
Pin
Function
D0-D3
Data Inputs
EN
Enable Input
Qna, Qnb
True Outputs
Qna, Qnb
Inverting Outputs
VCCO
VCC to Output
PIN NAMES
BLOCK DIAGRAM
EN
Q0a
Q0b
D0
Q0a
Q0b
Q1a
Q1b
D1
Q1a
Q1b
Q2a
Q2b
D2
Q2a
Q2b
Q3a
Q3b
D3
Q3a
Q3b
Rev.: G
Amendment: /0
Issue Date:
March 2006
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