VEE
參數(shù)資料
型號: SY100E016JC
廠商: Micrel Inc
文件頁數(shù): 5/10頁
文件大?。?/td> 0K
描述: IC UPCOUNTER 8BIT SYNC 28-PLCC
標(biāo)準(zhǔn)包裝: 38
系列: 100E
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向:
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
復(fù)位: 異步
計(jì)時(shí): 同步
計(jì)數(shù)速率: 900MHz
觸發(fā)器類型: 正邊沿
電源電壓: 4.2 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC
包裝: 管件
4
SY10E016
SY100E016
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = –40
°CTA = 0°CTA = +25°CTA = +85°C
Symbol
Parameter
Min.
Typ. Max. Min.
Typ.
Max. Min.
Typ. Max. Min.
Typ. Max.
Unit
IIH
Input HIGH Current
150
150
150
150
A
IEE
Power Supply Current
mA
10E
151
181
151
181
151
181
151
181
100E
151
181
151
181
151
181
174
208
TRUTH TABLE
(1)
CE
PE
TCLD
MR
CLK
Function
X
L
X
L
Z
Load Parallel (Pn to Qn)
L
H
L
Z
Continuous Count
L
H
L
Z
Count; Load Parallel on TC = LOW
H
X
L
Z
Hold
X
L
ZZ
Master respond, Slaves Hold
X
H
Z
Reset (Qn : = LOW, TC : = HIGH)
NOTE:
1. Z = Clock Pulse (LOW-to-HIGH), ZZ = Clock Pulse (HIGH-to-LOW)
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = –40
°CTA = 0°CTA = 25°CTA = +85°C
Symbol
Parameter
Min.
Typ. Max.
Min.
Typ.
Max.
Min.
Typ. Max. Min.
Typ. Max.
Unit
fCOUNT
Max. Count Frequency
700
900
700
900
700
900
700
900
MHz
tPD
Propagation Delay to Output
ps
CLK to Q
600
725
1000
600
725
1000
600
725
1000
600
725
1000
MR to Q
600
775
1000
600
775
1000
600
775
1000
600
775
1000
CLK to TC (Qs loaded)(1)
550
775
1050
550
775
1050
550
775
1050
550
775
1050
CLK to TC (Qs unloaded)(1)
550
700
900
550
700
900
550
700
900
550
700
900
MR to TC
625
775
1000
625
775
1000
625
775
1000
625
775
1000
tS
Set-up Time
ps
Pn
150
–30
150
–30
150
–30
150
–30
CE
600
400
600
400
600
400
600
400
PE
600
400
600
400
600
400
600
400
TCLD
500
300
500
300
500
300
500
300
tH
Hold Time
ps
Pn
250
30
250
30
250
30
250
30
CE
0
–400
0
–400
0
–400
0
–400
PE
0
–400
0
–400
0
–400
0
–400
TCLD
100
–300
100
–300
100
–300
100
–300
tRR
Reset Recovery Time
900
700
900
700
900
700
900
700
ps
tWP
Minimum Pulse Width
400
400
400
400
ps
CLK, MR
tr
Rise/Fall Times
300
510
800
300
510
800
300
510
800
300
510
800
ps
tf
20% to 80%
NOTE:
1. CLK to TC propagation delay is dependent on the loading of the Q outputs. With all of the Q outputs loaded, the noise generated in going from a IIII IIII
state to a 0000 0000 state causes the CLk to TC+ delay to increase.
AC ELECTRICAL CHARACTERISTICS
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