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參數(shù)資料
| 型號： | STV9426 |
| 廠商： | 意法半導體 |
| 英文描述： | MULTISYNC ON-SCREEN DISPLAY FOR MONITOR |
| 中文描述： | 多頻屏幕的監(jiān)視器顯示 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大小： | 184K |
| 代理商： | STV9426 |
FUNCTIONAL DESCRIPTION
(continued)
VI- User Definable Character
The STV9425/25B/26 allows the user to dynami-
cally define character(s) for his own needs (for a
specialLOGOforexample).LiketheROMcharac-
ters, a UDC is made of a 12 pixels x 18 slices dot
matrix, but one more slice is added for the vertical
shadowing when several UDCs are gathered to
makea specialgreat character (seeFigure 8).
In a UDC, each pixel is definedwith a bit, 1 refers
to foreground, and 0 to background color. Each
slice of a UDC uses 2 bytes :
add +
1
-
-
-
-
PX11 PX10 PX9
PX8
add
(even)
PX11is theleftmostpixel.Characterslice address:
SLICEADDRESS=38x(CHARACTERNUMBER)
+ (SLICE NUMBER).
Where :
- CHARACTER NUMBER is the number given by
the charactercode,
- SLICENUMBERis thenumbergiven bytheslice
interpolator (n
°
of the current slice of the strip :
1 < <18)
PX7 PX6 PX5 PX4 PX3 PX2 PX1 PX0
VII - ROMCharacter Generator
The STV9425/25B/26 includes a ROM character
generator which is made of 128 alphanumeric or
graphiccharacters(see Table1)
VIII - PLL
ThePLL functionof theSTV9425/25B/26provides
the internal pixel clock locked on the horizontal
synchro signal and used by the display processor
to generatethe R, G,B and fast blanckingsignals.
It is made of 2 PLLs.
(see Figure 9), provides a high frequency signal
locked on the crystal frequency. The frequency
multiplier is given by :
N = 2
(FM[3:0]+ 3)
Where FM[3:0] is the value of the FREQUENCY
MULTIPLIERregister.
The first one analogic
FILTRE
%N
F
XTAL
VCO
N.F
XTAL
9
Figure 9 :
AnalogicPLL
The second PLL, full digital (see Figure 10), pro-
vides a pixel frequency locked on the horizontal
synchrosignal. The ratio betweenthe frequencies
of these 2 signalsis :
M = 12 x (LD[5:0]+ 1)
WhereLD[5:0]isthevalueof the LINEDURATION
register.
ALGO
%M
F
H-SYNC
%D
M.F
H-SYNC
err(n)
D(n)
N.F
XTAL
9
Figure 10 :
Digital PLL
VIII.1 - Programming of the PLL Registers
FrequencyMultiplier
(@3FF7)
This register gives the ratio between the crystal
frequency and the high frequency of the signal
usedbythe2
nd
PLLtoprovide,bydivision,thepixel
clock. The value of this high frequency must be
near to 200MHz (for example if the crystal is a
8MHz, the value of FM must be equal to 10) and
greaterthan6 x (pixel frequency).
Initial Pixel Period
(@3FF6)
This register allows to increase the speed of the
convergence of the PLL when the horizontal fre-
quencychanges(new graphic standart).The rela-
tionshipbetweenFM[3:0],PP[7:0],LD[5:0],F
HSYNC
and F
XTAL
is :
PP[7:0]
=
round
Locking Condition TimeConstant
(@ 3FF4)
This register gives the constants AS[2:0] and
BS[2:0]usedbythealgopartof thePLL(seeFigure
10) to calculate, from the phase error, err(n), the
new value, D(n), of the division of the high fre-
quencysignaltoprovidethe pixelclock.Thesetwo
constantsare usedonlyin lockingcondition,which
is true, if the phaseerror is less thana fixed value
during at least, 4 scan lines. If the phase error
becomes greater than the fixed value, the PLL is
not in locking condition but in capture process. In
this case, the algo part of the PLL used the other
constants,AF[2:0] and BF[2:0], given by the next
register.
Capture ProcessTime Constant
(@ 3FF5)
The choice between these two time constants
(locking condition or capture process) allows to
decreasethecaptureprocesstimebychangingthe
time responseof the PLL.
8
2
(
FM[3:0]
+
3
)
F
XTAL
12
(
LD[5:0]
+
1
)
F
HSYNC
24
STV9425 - STV9425B - STV9426
12/15
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