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參數(shù)資料
| 型號(hào)： | STV9422 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | MULTISYNC ON-SCREEN DISPLAY FOR MONITOR |
| 中文描述： | 多頻屏幕的監(jiān)視器顯示 |
| 文件頁(yè)數(shù)： | 12/15頁(yè) |
| 文件大?。?/td> | 232K |
| 代理商： | STV9422 |
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FUNCTIONAL DESCRIPTION
(continued)
VI - User Definable Character
The STV9422/24 allows the user to dynamically
define character(s)for his ownneeds(fora special
LOGO for example). Like the ROM characters, a
UDC is made of a 12 pixelsx 18 slices dot matrix,
but one more slice is added for the vertical shad-
owing when several UDCs are gatheredto makea
special greatcharacter (see Figure 8).
In a UDC,each pixel is defined with a bit,1 refers
to foreground, and 0 to background color. Each
slice of aUDC uses 2 bytes:
add +
1
-
-
-
-
PX11 PX10 PX9
PX8
add
(even)
PX11is the left most pixel. Characterslice address:
SLICEADDRESS=38x(CHARACTERNUMBER)
+ (SLICE NUMBER).
Where :
- CHARACTER NUMBER is the number given by
the character code,
- SLICE NUMBER isthe number givenbythe slice
interpolator (n
°
of the current slice of the strip :
1 < <18)
PX7 PX6 PX5 PX4 PX3 PX2 PX1 PX0
VII - ROM Character Generator
The STV9422/24includes a ROM character gen-
erator which is made of 128 alphanumeric or
graphic characters (seeTable 1)
VIII - PLL
The PLL function of the STV9422/24provides the
internalpixelclocklockedonthehorizontalsynchro
signal and usedby thedisplay processorto gener-
ate theR,G,Bandfast blanckingsignals.Itismade
of 2 PLLs. The first one analogic (see Figure 9),
provides a high frequency signal locked on the
crystal frequency.The frequencymultiplieris given
by :
N = 2
(FM[3:0] + 3)
Where FM[3:0] is the value of the FREQUENCY
MULTIPLIER register.
FILTRE
%N
F
XTAL
VCO
N.F
XTAL
9
Figure 9 :
AnalogicPLL
The second PLL, full digital (see Figure 10), pro-
vides a pixel frequency locked on the horizontal
synchrosignal. The ratio between the frequencies
of these 2 signalsis :
M = 12 x (LD[5:0] + 1)
Where LD[5:0]is the value of the LINEDURATION
register.
ALGO
%M
F
H-SYNC
%D
M.F
H-SYNC
err(n)
D(n)
N.F
XTAL
9
Figure 10 :
Digital PLL
VIII.1 - Programming of the PLLRegisters
Frequency Multiplier
(@3FF7)
This register gives the ratio between the crystal
frequency and the high frequency of the signal
usedbythe2
nd
PLLto provide,bydivision,thepixel
clock. The value of this high frequency must be
near to 200MHz (for example if the crystal is a
8MHz, the value of FM must be equal to 10) and
greaterthan 6x (pixel frequency).
Initial Pixel Period
(@3FF6)
This register allows to increase the speed of the
convergence of the PLL when the horizontal fre-
quencychanges(new graphicstandart). The rela-
tionshipbetweenFM[3:0], PP[7:0],LD[5:0],F
HSYNC
and F
XTAL
is :
PP[7:0]
=
round
Locking Condition Time Constant
(@3FF4)
This register gives the constants AS[2:0] and
BS[2:0]usedbythealgopartof thePLL(seeFigure
10) to calculate, from the phase error, err(n), the
new value, D(n), of the division of the high fre-
quencysignal to providethe pixel clock. Thesetwo
constantsare usedonly in lockingcondition,which
is true, if thephase error is less than a fixedvalue
during at least, 4 scan lines. If the phase error
becomes greater than the fixed value, the PLL is
not in locking condition but in capture process. In
this case, the algo part of the PLL used the other
constants, AF[2:0] and BF[2:0], given by the next
register.
Capture Process TimeConstant
(@3FF5)
The choice between these two time constants
(locking condition or capture process) allows to
decreasethecaptureprocesstimebychangingthe
time response of the PLL.
8
2
(
FM[3:0]
+
3
)
F
XTAL
12
(
LD[5:0]
+
1
)
F
HSYNC
±
24
STV9422 - STV9424
12/15
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|---|---|
| STV9422S | 制造商:STMicroelectronics 功能描述: |
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| STV9425B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MULTISYNC ON-SCREEN DISPLAY FOR MONITOR |
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