參數(shù)資料
型號(hào)： STV9410D
廠(chǎng)商： 意法半導(dǎo)體
英文描述： CONNECTOR ACCESSORY
中文描述： 連接器附件
文件頁(yè)數(shù)： 14/25頁(yè)
文件大小： 262K
代理商： STV9410D
2.3.2. CRTMode
In CRTmode, the Vsyncsignal appearsat thefirst
two lines of the first strip of the descriptor list. It is
recommendedto providean uniform blanked(with
FFB bit) strip as first descriptor. The scan line
number of thisstrip haveto beequal orhigher than
scan line number of the verticalblanking Interval.
Master Mode
This mode is selectedby writing VSE and HSE bit
of VERT register with logical value ”0”.
Non-interlaced
mode is selectedbywritingILCbit
of VERT register with logical value ”0”.
Horizontal or composite synchronization signal is
output on C
SYNC
pin, Vertical synchronization sig-
nal is output on V
SYNC
pin.
Signal waveforms are described in Figure9.
Interlaced
mode is selected by writing ILC bit of
VERT register with logical value ”1”.
Even frame is identical to non-interlaced frame.
V
SYNC
PULSEis low during secondhalf of last line
of previousOddframeandduringthetwo first lines
of current Even frame.
Odd frame is one scan line morethan Evenframe.
V
SYNC
PULSEis low during the two first lines and
up tofirst halfof the thirdline of current Oddframe.
Half line corresponds to 17th character position.
Signalswaveforms are describedin Figure10.
Slave Mode
This mode is activatedby writing VSE and/or HSE
bit of VERT register with logical value ”1”. Then
SYNC IN input signal is sampled according to
proceduredescribedbelow.
VerticalSynchronization
SYNC IN signal may beeither a vertical synchroni-
zation or a composite synchronization. It is sam-
pled on first pixel of eachscan lineactive area. As
soon as SYNC IN signal low level is detected,
Figure 9
: ODDand EVENSynchronizationPulses in Non-interlacedMode
vertical time base counter F(8:0) of VERTregister
is reset withoutany modificationof othertime base
registers.
Horizontal Synchronization
SYNC IN is sampled one pxlck before and one
pxlck after internal horizontal pulse transition. If
falling edge is not found,one pixel period is added
to internal line duration. Using a line frequency
locked clock applied on XTI, internal scan line
becomes phaselockedafter few scan line periods
at programmedvalue (see Figure11).
2.3.3 LCD Mode
LCD mode only works as a master mode with 320
pixels per line. Internal algorithm allows 8 grey
levels on passive LCD matrix. Numberof scan line
is programmable.In order to get maximum refresh
frequencyofdisplay, marginandline durationmust
be reduced to miminum. Interlacedmode and ex-
ternal synchronizationare not allowed. The 1
st
line
of the first descriptor in the description list corre-
spond to the first line of the LCD display. Y output
provides a programmablevoltage usable to adjust
contrast of LCD display. To reduce supply current
consumption,whenY output isunused,V
SSA
must
not be connectedto ground,and V
REF
pinworksas
a reset pin. Notice that SYNC IN Pin provides
(CKD) data clock signal.
2.4 POROUTPUT
POR is a standardI/O pinprogrammableat logical
level”1” or”0”. Itcan alsoprovidea programmable
square wave signal of period
P = 16 x N(7:0)x pxlck (0
≤
N
≤
255).
It can drive a capacitive buzzer (see application
diagram at page 22).
RESETvalue of PORTis ”0”.
H SYNCPULSE
C
V
”VERT” LSB REG
LINE NUMBER
N
N + 1
N + 2
F0
F1
1
2
F2
3
F3
4
HorizontalSynchro
CompositeSynchro
Vertical Synchro
Programmedvalue
of F (8 : 0) is N
Framenumber
of lines is N + 2
DESIGNATION
TIMING DIAGRAM
COMMENTS
F
N - 1
F
N
F
N + 1
*
* Internal logic adds one more line
PULSE
SYNC
SYNC
PULSE
9
STV9410
14/25
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