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參數(shù)資料
| 型號(hào)： | STV7697WAF |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | PLASMA DISPLAY PANEL SCAN DRIVER |
| 中文描述： | 等離子顯示器掃描驅(qū)動(dòng) |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 110K |
| 代理商： | STV7697WAF |
STV7697A
10/15
3
AC TIMINGS REQUIREMENTS
(V
CC
= 4.5 V to 5.5 V, T
amb
= -20 to +85
°
C, input signals max leading edge & trailing edge (t
R
, t
F
) = 10 ns)
AC TIMINGS CHARACTERISTICS
(V
CC
= 5 V, V
PP
= 90 V
,
V
SSP
= 0 V, V
SSLOG
= V
SSSUB
= 0 V, T
amb
= 25
°
C, f
CLK
= 20 MHz, V
ILMax.
= 0.2
Vcc, V
IHMin.
= 0.8 V
CC
, V
OH
= 4.0 V,V
OL
= 0.4 V, C
L
= 15pF, unless otherwise specified)
Note 7
One output among 64, loading capacitor C
OUT
= 100pF, other outputs at low level.
Symbol
Parameter
Min.
Typ.
Max.
Unit
t
CLK
Data Clock Period
50
-
-
ns
t
WHCLK
Duration of clock (CLK) pulse at high level
15
-
-
ns
t
WHCLK
t
SDAT
Duration of clock (CLK) pulse at low level
15
-
-
ns
Set-up Time of data input before clock low to high transition
10
-
-
ns
t
HDAT
Hold Time of data input after clock low to high transition
10
-
-
ns
t
SFR
Forward/reverse (F/R) Set-up Time before low to high transition
100
-
-
ns
t
DSTB
Minimum Delay to latch STB after clock low to high transition
10
-
-
ns
t
STB
Strobe STB Pulse Duration
20
-
-
ns
t
BLK
Blank (BLK) Pulse Duration
500
-
-
ns
t
POL
Polarity (POL) Pulse Duration
500
-
-
ns
Symbol
Parameter
Min.
Typ.
Max.
Unit
t
CLK
Data Clock Period
50
-
-
ns
t
RDAT
t
FDAT
t
PHL1
t
PLH1
Logical Data Output Rise Time
Logical Data Output Fall Time
-
-
20
11
-
-
ns
ns
Delay of logic data output after clock (CLK) high to low transition
Delay of logic data output after clock (CLK) low to high transition
-
-
45
48
80
80
ns
ns
t
PHL2
t
PLH2
Delay of power output change after clock (CLK) high to low transition
Delay of power output change after clock (CLK) low to high transition
-
-
120
120
180
180
ns
ns
t
PHL3
t
PLH3
Delay of power output change after blanking (BLK) high to low transition
Delay of power output change after blanking (BLK) low to high transition
-
-
110
110
165
165
ns
ns
t
PHL4
t
PLH4
Delay of power output change after polarity (POL) high to low transition
Delay of power output change after polarity (POL) low to high transition
-
-
-
-
160
160
ns
ns
t
ROUT
t
FOUT
Power Output Rise Time (7)
Power Output Fall Time (7)
-
-
100
60
200
200
ns
ns
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