參數(shù)資料
型號: STV7697A
廠商: 意法半導(dǎo)體
英文描述: PLASMA DISPLAY PANEL SCAN DRIVER
中文描述: 等離子顯示器掃描驅(qū)動
文件頁數(shù): 7/15頁
文件大?。?/td> 110K
代理商: STV7697A
STV7697A
7/15
BLOCK DIAGRAM
CIRCUIT DESCRIPTION
The STV7697A contains all the logic and the pow-
er circuits necessary to drive rows of a Plasma
Display Panel (P.D. P.). The state of the displayed
line is loaded into the shift register. Data are shift-
ed at each low to high transition of the (CLK) shift
clock. After 64 shifts the first bit is available at the
serial output. This output can be used to cascade
several drivers to perform any vertical resolution.
The forward / reverse (F/R) input is used to select
the direction of the shift register, data input/output
status is set according to the selected direction.
SIN, CLK, STB inputs
are Smith trigger inputs . If not used on the appli-
cation, F/R, BLK, POL logical inputs are internaly
pulled to level ”1”. The maximum frequency of the
shift clock is 20 MHz.
All the data are memorized into the latch stage
when the strobe input (STB) is pulled high.
Blanking input (BLK) forces the power outputs to
high level when pulled high with polarity input
(POL) at high level and forced to low level with
POL at low level.
The level of the power output is inverted when the
polarity command (POL) is pulled high.
Sustain current must not be sunk in the powerout-
put to V
PP
when the power supply is applied.
V
SSLOG
and V
SSSUB
must be connected as close
as possible to the logical reference ground of the
application.
Shift Register Truth Table
F/R
87
64-BITSHIFT REGISTER
P1
P64
80
1
V
Pins34-35-36-45-46
47-82-83-98-99
V
Pins41-90
V
Pins39-40-42-94
SOUT(SIN)
SIN(SOUT)
STB
BLK
POL
OUT1
OUT64
STV7697A
93
91
92
86
85
89
CLK
V
Pins33-37-44-48
81-84-97-100
LATCH
Q1
Q64
Q2
Q63
S64
S1
V
CC
V
CC
V
CC
V
Pins38-43
V
SSP
V
PP
V
SSP
V
PP
-
-
Input
Input/Output
Shift Register
Function
F/R
CLK
SIN
SOUT
Output Q
H
Rise
IN
OUT
Forward Shift
H
H or L
IN
OUT
Steady
L
Rise
OUT
IN
Reverse Shift
L
H or L
OUT
IN
Steady
3
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