
F/R
87
64-BIT SHIFT REGISTER
P1
P64
80
1
V
Pins34-35-36-45-46
47-82-83-98-99
V
Pins41-90
V
Pins39-40-42-94
SOUT(SIN)
SIN (SOUT)
STB
BLK
POL
OUT1
OUT64
STV7697
93
91
92
86
85
89
CLK
V
Pins33-37-44-49
81-84-97-100
LATCH
Q1
Q64
Q2
Q63
S64
S1
V
CC
V
CC
V
CC
V
Pins38-43
V
SSP
V
PP
V
SSP
V
PP
7
BLOCKDIAGRAM
CIRCUIT DESCRIPTION
The STV7697 containsall the logic and the power
circuits necessary to drive rows of a Plasma Dis-
playPanel(P.D. P.).Thestateof thedisplayedline
is loaded into the shift register. Data are shifted at
eachlow to high transitionof the(CLK) shiftclock.
After 64 shifts the first bit is availableat the serial
output.Thisoutputcan beusedto cascadeseveral
drivers to performany vertical resolution.
The forward/reverse (F/R) input is used to select
the direction of the shift register, data input/output
status is set according to the selected direction.
SIN, CLK, STB inputs are Smith trigger inputs .
If not used on the application,F/R, BLK,POL logi-
cal inputs are internaly pulled to level ”1”. The
maximum frequencyof the shiftclock is 20MHz.
All the the data arememorizedinto the latchstage
when the strobeinput (STB) is pulled high.
Blanking input (BLK) forces the power outputs to
highlevelwhenpulledhighwithpolarityinput(POL)
at highleveland forcedtolow levelwithPOLat low
level.
The level of the power output is invertedwhen the
polaritycommand (POL) is pulledhigh.
Sustain current must not be sunk in the power
output to V
PP
when the power supply is applied.
V
SSLOG
andV
SSSUB
mustbe connectedas closeas
possible to the logical reference ground of the
application.
Shift RegisterTruth Table
Input
Input/Output
Shift Register
Function
Output Q
Forward shift
Steady
Reverse Shift
Steady
F/R
H
H
L
L
CLK
Rise
H or L
Rise
H or L
SIN
IN
IN
OUT
OUT
SOUT
OUT
OUT
IN
IN
PowerOutput TruthTable
Qn (1)
STB
X
X
X
X
H
L
L
L
H
L
L
L
X
H
X
H
BLK
H
H
L
L
L
L
L
L
POL
H
L
L
L
H
H
L
H
Driver Output
All H
All L
H
L
L
H
Qn
Qn
Comments
Forced to High
Forced to Low
Copy Data
Copy Data
Copy Inverted Data
Copy Inverted Data
Data Latched
Inverted Data Latched
Note :
1. Qn is the parallel output of the shift register (n = 1 to 64). Qn takes the value of serial input(SIN) after ”n” shiftclock periods.
STV7697
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